Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 3c997d24 authored by Eric Huang's avatar Eric Huang Committed by Alex Deucher
Browse files

drm/amdgpu: add sdma clock gating support for Fiji. 



Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarJammy Zhou <Jammy.Zhou@amd.com>
Signed-off-by: default avatarEric Huang <JinHuiEric.Huang@amd.com>
parent a0d69786

drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

+105 −0
Original line number Diff line number Diff line
@@ -1429,9 +1429,114 @@ static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev, 
	return 0;

}



static void fiji_update_sdma_medium_grain_clock_gating(

		struct amdgpu_device *adev,

		bool enable)

{

	uint32_t temp, data;



	if (enable) {

		temp = data = RREG32(mmSDMA0_CLK_CTRL);

		data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);

		if (data != temp)

			WREG32(mmSDMA0_CLK_CTRL, data);



		temp = data = RREG32(mmSDMA1_CLK_CTRL);

		data &= ~(SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK);



		if (data != temp)

			WREG32(mmSDMA1_CLK_CTRL, data);

	} else {

		temp = data = RREG32(mmSDMA0_CLK_CTRL);

		data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |

				SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;



		if (data != temp)

			WREG32(mmSDMA0_CLK_CTRL, data);



		temp = data = RREG32(mmSDMA1_CLK_CTRL);

		data |= SDMA1_CLK_CTRL__SOFT_OVERRIDE7_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE6_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE5_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE4_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE3_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE2_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE1_MASK |

				SDMA1_CLK_CTRL__SOFT_OVERRIDE0_MASK;



		if (data != temp)

			WREG32(mmSDMA1_CLK_CTRL, data);

	}

}



static void fiji_update_sdma_medium_grain_light_sleep(

		struct amdgpu_device *adev,

		bool enable)

{

	uint32_t temp, data;



	if (enable) {

		temp = data = RREG32(mmSDMA0_POWER_CNTL);

		data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;



		if (temp != data)

			WREG32(mmSDMA0_POWER_CNTL, data);



		temp = data = RREG32(mmSDMA1_POWER_CNTL);

		data |= SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;



		if (temp != data)

			WREG32(mmSDMA1_POWER_CNTL, data);

	} else {

		temp = data = RREG32(mmSDMA0_POWER_CNTL);

		data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;



		if (temp != data)

			WREG32(mmSDMA0_POWER_CNTL, data);



		temp = data = RREG32(mmSDMA1_POWER_CNTL);

		data &= ~SDMA1_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;



		if (temp != data)

			WREG32(mmSDMA1_POWER_CNTL, data);

	}

}



static int sdma_v3_0_set_clockgating_state(void *handle,

					  enum amd_clockgating_state state)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)handle;



	switch (adev->asic_type) {

	case CHIP_FIJI:

		fiji_update_sdma_medium_grain_clock_gating(adev,

				state == AMD_CG_STATE_GATE ? true : false);

		fiji_update_sdma_medium_grain_light_sleep(adev,

				state == AMD_CG_STATE_GATE ? true : false);

		break;

	default:

		break;

	}

	return 0;

}