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Commit 3c0edaeb authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter
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drm/i915: Drop WaDisableRCPBUnitClockGating:vlv 



Only early VLV steppings needed thist. Should no longer be relevant.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent d1561c29

drivers/gpu/drm/i915/intel_pm.c

+3 −11
Original line number Diff line number Diff line
@@ -4928,24 +4928,16 @@ static void valleyview_init_clock_gating(struct drm_device *dev) 
		   I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |

		   GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);



	/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock

	 * gating disable must be set.  Failure to set it results in

	 * flickering pixels due to Z write ordering failures after

	 * some amount of runtime in the Mesa "fire" demo, and Unigine

	 * Sanctuary and Tropics, and apparently anything else with

	 * alpha test or pixel discard.

	 *

	/*

	 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.

	 * This implements the WaDisableRCZUnitClockGating:vlv workaround.

	 *

	 * Also apply WaDisableVDSUnitClockGating:vlv and

	 * WaDisableRCPBUnitClockGating:vlv.

	 * Also apply WaDisableVDSUnitClockGating:vlv.

	 */

	I915_WRITE(GEN6_UCGCTL2,

		   GEN7_VDSUNIT_CLOCK_GATE_DISABLE |

		   GEN7_TDLUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE |

		   GEN6_RCPBUNIT_CLOCK_GATE_DISABLE);

		   GEN6_RCZUNIT_CLOCK_GATE_DISABLE);



	/* WaDisableL3Bank2xClockGate:vlv */

	I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);