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Commit 3b2e7c7c authored by John Crispin's avatar John Crispin Committed by Ralf Baechle
Browse files

MIPS: ralink: Add a few missing clocks 



Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/11995/


Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 3bca798b

arch/mips/ralink/mt7620.c

+3 −0
Original line number Diff line number Diff line
@@ -456,7 +456,10 @@ void __init ralink_clk_init(void) 
	ralink_clk_add("10000100.timer", periph_rate);

	ralink_clk_add("10000120.watchdog", periph_rate);

	ralink_clk_add("10000b00.spi", sys_rate);

	ralink_clk_add("10000b40.spi", sys_rate);

	ralink_clk_add("10000c00.uartlite", periph_rate);

	ralink_clk_add("10000d00.uart1", periph_rate);

	ralink_clk_add("10000e00.uart2", periph_rate);

	ralink_clk_add("10180000.wmac", xtal_rate);



	if (IS_ENABLED(CONFIG_USB) && !is_mt76x8()) {

arch/mips/ralink/rt305x.c

+1 −0
Original line number Diff line number Diff line
@@ -201,6 +201,7 @@ void __init ralink_clk_init(void) 
	ralink_clk_add("cpu", cpu_rate);

	ralink_clk_add("sys", sys_rate);

	ralink_clk_add("10000b00.spi", sys_rate);

	ralink_clk_add("10000b40.spi", sys_rate);

	ralink_clk_add("10000100.timer", wdt_rate);

	ralink_clk_add("10000120.watchdog", wdt_rate);

	ralink_clk_add("10000500.uart", uart_rate);

arch/mips/ralink/rt3883.c

+1 −0
Original line number Diff line number Diff line
@@ -109,6 +109,7 @@ void __init ralink_clk_init(void) 
	ralink_clk_add("10000120.watchdog", sys_rate);

	ralink_clk_add("10000500.uart", 40000000);

	ralink_clk_add("10000b00.spi", sys_rate);

	ralink_clk_add("10000b40.spi", sys_rate);

	ralink_clk_add("10000c00.uartlite", 40000000);

	ralink_clk_add("10100000.ethernet", sys_rate);

	ralink_clk_add("10180000.wmac", 40000000);