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Commit 3ace822a authored by Marek Vasut's avatar Marek Vasut Committed by Greg Kroah-Hartman
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serial: 8250: Add missing rxtrig_bytes on Altera 16550 UART 



The Altera 16550 UART core supports FCR Rx Trigger Level setting,
but the port definition in the driver is missing the rxtrig_bytes
array specifying the trigger levels. Add the array to make the Rx
Trigger Level setting available on this type of 16550 UART.

Signed-off-by: default avatarMarek Vasut <marex@denx.de>
Cc: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a451debb

drivers/tty/serial/8250/8250_port.c

+3 −0
Original line number Diff line number Diff line
@@ -243,6 +243,7 @@ static const struct serial8250_config uart_config[] = { 
		.fifo_size	= 32,

		.tx_loadsz	= 32,

		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,

		.rxtrig_bytes	= {1, 8, 16, 30},

		.flags		= UART_CAP_FIFO | UART_CAP_AFE,

	},

	[PORT_ALTR_16550_F64] = {
@@ -250,6 +251,7 @@ static const struct serial8250_config uart_config[] = { 
		.fifo_size	= 64,

		.tx_loadsz	= 64,

		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,

		.rxtrig_bytes	= {1, 16, 32, 62},

		.flags		= UART_CAP_FIFO | UART_CAP_AFE,

	},

	[PORT_ALTR_16550_F128] = {
@@ -257,6 +259,7 @@ static const struct serial8250_config uart_config[] = { 
		.fifo_size	= 128,

		.tx_loadsz	= 128,

		.fcr		= UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,

		.rxtrig_bytes	= {1, 32, 64, 126},

		.flags		= UART_CAP_FIFO | UART_CAP_AFE,

	},

	/*