Merge tag 'pci-v4.18-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci (3a3869f1) · Commits · e / devices / android_kernel_teracube_emerald

Documentation/PCI/pci-error-recovery.txt

+25 −10

Original line number	Diff line number	Diff line
		@@ -110,7 +110,7 @@ The actual steps taken by a platform to recover from a PCI error
		event will be platform-dependent, but will follow the general
		sequence described below.

		STEP 0: Error Event
		STEP 0: Error Event: ERR_NONFATAL
		-------------------
		A PCI bus error is detected by the PCI hardware. On powerpc, the slot
		is isolated, in that all I/O is blocked: all reads return 0xffffffff,
		@@ -228,13 +228,7 @@ proceeds to either STEP3 (Link Reset) or to STEP 5 (Resume Operations).
		If any driver returned PCI_ERS_RESULT_NEED_RESET, then the platform
		proceeds to STEP 4 (Slot Reset)

		STEP 3: Link Reset
		------------------
		The platform resets the link. This is a PCI-Express specific step
		and is done whenever a fatal error has been detected that can be
		"solved" by resetting the link.

		STEP 4: Slot Reset
		STEP 3: Slot Reset
		------------------

		In response to a return value of PCI_ERS_RESULT_NEED_RESET, the
		@@ -320,7 +314,7 @@ Failure).
		>>> However, it probably should.


		STEP 5: Resume Operations
		STEP 4: Resume Operations
		-------------------------
		The platform will call the resume() callback on all affected device
		drivers if all drivers on the segment have returned
		@@ -332,7 +326,7 @@ a result code.
		At this point, if a new error happens, the platform will restart
		a new error recovery sequence.

		STEP 6: Permanent Failure
		STEP 5: Permanent Failure
		-------------------------
		A "permanent failure" has occurred, and the platform cannot recover
		the device. The platform will call error_detected() with a
		@@ -355,6 +349,27 @@ errors. See the discussion in powerpc/eeh-pci-error-recovery.txt
		for additional detail on real-life experience of the causes of
		software errors.

		STEP 0: Error Event: ERR_FATAL
		-------------------
		PCI bus error is detected by the PCI hardware. On powerpc, the slot is
		isolated, in that all I/O is blocked: all reads return 0xffffffff, all
		writes are ignored.

		STEP 1: Remove devices
		--------------------
		Platform removes the devices depending on the error agent, it could be
		this port for all subordinates or upstream component (likely downstream
		port)

		STEP 2: Reset link
		--------------------
		The platform resets the link. This is a PCI-Express specific step and is
		done whenever a fatal error has been detected that can be "solved" by
		resetting the link.

		STEP 3: Re-enumerate the devices
		--------------------
		Initiates the re-enumeration.

		Conclusion; General Remarks
		---------------------------

Documentation/admin-guide/kernel-parameters.txt

+2 −0

Original line number	Diff line number	Diff line
		@@ -3162,6 +3162,8 @@
		on: Turn realloc on
		realloc same as realloc=on
		noari do not use PCIe ARI.
		noats [PCIE, Intel-IOMMU, AMD-IOMMU]
		do not use PCIe ATS (and IOMMU device IOTLB).
		pcie_scan_all Scan all possible PCIe devices. Otherwise we
		only look for one device below a PCIe downstream
		port.

Documentation/devicetree/bindings/pci/designware-pcie.txt

+18 −6

Original line number	Diff line number	Diff line
		* Synopsys DesignWare PCIe interface

		Required properties:
		- compatible: should contain "snps,dw-pcie" to identify the core.
		- compatible:
		"snps,dw-pcie" for RC mode;
		"snps,dw-pcie-ep" for EP mode;
		- reg: Should contain the configuration address space.
		- reg-names: Must be "config" for the PCIe configuration space.
		(The old way of getting the configuration address space from "ranges"
		@@ -41,11 +43,11 @@ EP mode:

		Example configuration:

		pcie: pcie@dffff000 {
		pcie: pcie@dfc00000 {
		compatible = "snps,dw-pcie";
		reg = <0xdffff000 0x1000>, /* Controller registers */
		<0xd0000000 0x2000>; /* PCI config space */
		reg-names = "ctrlreg", "config";
		reg = <0xdfc00000 0x0001000>, /* IP registers */
		<0xd0000000 0x0002000>; /* Configuration space */
		reg-names = "dbi", "config";
		#address-cells = <3>;
		#size-cells = <2>;
		device_type = "pci";
		@@ -54,5 +56,15 @@ Example configuration:
		interrupts = <25>, <24>;
		#interrupt-cells = <1>;
		num-lanes = <1>;
		num-viewport = <3>;
		};
		or
		pcie: pcie@dfc00000 {
		compatible = "snps,dw-pcie-ep";
		reg = <0xdfc00000 0x0001000>, /* IP registers 1 */
		<0xdfc01000 0x0001000>, /* IP registers 2 */
		<0xd0000000 0x2000000>; /* Configuration space */
		reg-names = "dbi", "dbi2", "addr_space";
		num-ib-windows = <6>;
		num-ob-windows = <2>;
		num-lanes = <1>;
		};

Documentation/devicetree/bindings/pci/mobiveil-pcie.txt

0 → 100644

+73 −0

Original line number	Diff line number	Diff line
		* Mobiveil AXI PCIe Root Port Bridge DT description

		Mobiveil's GPEX 4.0 is a PCIe Gen4 root port bridge IP. This configurable IP
		has up to 8 outbound and inbound windows for the address translation.

		Required properties:
		- #address-cells: Address representation for root ports, set to <3>
		- #size-cells: Size representation for root ports, set to <2>
		- #interrupt-cells: specifies the number of cells needed to encode an
		interrupt source. The value must be 1.
		- compatible: Should contain "mbvl,gpex40-pcie"
		- reg: Should contain PCIe registers location and length
		"config_axi_slave": PCIe controller registers
		"csr_axi_slave" : Bridge config registers
		"gpio_slave" : GPIO registers to control slot power
		"apb_csr" : MSI registers

		- device_type: must be "pci"
		- apio-wins : number of requested apio outbound windows
		default 2 outbound windows are configured -
		1. Config window
		2. Memory window
		- ppio-wins : number of requested ppio inbound windows
		default 1 inbound memory window is configured.
		- bus-range: PCI bus numbers covered
		- interrupt-controller: identifies the node as an interrupt controller
		- #interrupt-cells: specifies the number of cells needed to encode an
		interrupt source. The value must be 1.
		- interrupt-parent : phandle to the interrupt controller that
		it is attached to, it should be set to gic to point to
		ARM's Generic Interrupt Controller node in system DT.
		- interrupts: The interrupt line of the PCIe controller
		last cell of this field is set to 4 to
		denote it as IRQ_TYPE_LEVEL_HIGH type interrupt.
		- interrupt-map-mask,
		interrupt-map: standard PCI properties to define the mapping of the
		PCI interface to interrupt numbers.
		- ranges: ranges for the PCI memory regions (I/O space region is not
		supported by hardware)
		Please refer to the standard PCI bus binding document for a more
		detailed explanation


		Example:
		++++++++
		pcie0: pcie@a0000000 {
		#address-cells = <3>;
		#size-cells = <2>;
		compatible = "mbvl,gpex40-pcie";
		reg = <0xa0000000 0x00001000>,
		<0xb0000000 0x00010000>,
		<0xff000000 0x00200000>,
		<0xb0010000 0x00001000>;
		reg-names = "config_axi_slave",
		"csr_axi_slave",
		"gpio_slave",
		"apb_csr";
		device_type = "pci";
		apio-wins = <2>;
		ppio-wins = <1>;
		bus-range = <0x00000000 0x000000ff>;
		interrupt-controller;
		interrupt-parent = <&gic>;
		#interrupt-cells = <1>;
		interrupts = < 0 89 4 >;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 0 &pci_express 0>,
		<0 0 0 1 &pci_express 1>,
		<0 0 0 2 &pci_express 2>,
		<0 0 0 3 &pci_express 3>;
		ranges = < 0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;

		};

Documentation/devicetree/bindings/pci/pci-armada8k.txt

+4 −1

Original line number	Diff line number	Diff line
		@@ -12,7 +12,10 @@ Required properties:
		- "ctrl" for the control register region
		- "config" for the config space region
		- interrupts: Interrupt specifier for the PCIe controler
		- clocks: reference to the PCIe controller clock
		- clocks: reference to the PCIe controller clocks
		- clock-names: mandatory if there is a second clock, in this case the
		name must be "core" for the first clock and "reg" for the second
		one

		Example: