Commit 37ef0341 authored Jan 25, 2016 by Paul E. McKenney

documentation: Add alternative release-acquire outcome



The memory-barriers.txt discussion of local transitivity and
release-acquire chains leaves out discussion of the outcome of
the read from "u".  This commit therefore adds an outcome showing
that you can get a "1" from this read even if the release-acquire
pairs don't line up.

Reported-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>

parent c535cc92

Documentation/memory-barriers.txt

+4 −0

Original line number	Diff line number	Diff line
		@@ -1372,6 +1372,10 @@ is possible:

		r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0

		As an aside, the following outcome is also possible:

		r0 == 0 && r1 == 1 && r2 == 1 && r3 == 0 && r4 == 0 && r5 == 1

		Although cpu0(), cpu1(), and cpu2() will see their respective reads and
		writes in order, CPUs not involved in the release-acquire chain might
		well disagree on the order. This disagreement stems from the fact that