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Commit 37a0c6f9 authored by Pavel Machek's avatar Pavel Machek Committed by Mauro Carvalho Chehab
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media: omap3isp: Correctly set IO_OUT_SEL and VP_CLK_POL for CCP2 mode 



ISP CSI1 module needs all the bits correctly set to work.

Signed-off-by: default avatarIvaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Signed-off-by: default avatarPavel Machek <pavel@ucw.cz>
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> # on Beagleboard-xM + MPT9P031
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent 9211434b

drivers/media/platform/omap3isp/ispccp2.c

+5 −2
Original line number Diff line number Diff line
@@ -213,14 +213,17 @@ static int ccp2_phyif_config(struct isp_ccp2_device *ccp2, 
	struct isp_device *isp = to_isp_device(ccp2);

	u32 val;



	/* CCP2B mode */

	val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL) |

			    ISPCCP2_CTRL_IO_OUT_SEL | ISPCCP2_CTRL_MODE;

			    ISPCCP2_CTRL_MODE;

	/* Data/strobe physical layer */

	BIT_SET(val, ISPCCP2_CTRL_PHY_SEL_SHIFT, ISPCCP2_CTRL_PHY_SEL_MASK,

		buscfg->phy_layer);

	BIT_SET(val, ISPCCP2_CTRL_IO_OUT_SEL_SHIFT,

		ISPCCP2_CTRL_IO_OUT_SEL_MASK, buscfg->ccp2_mode);

	BIT_SET(val, ISPCCP2_CTRL_INV_SHIFT, ISPCCP2_CTRL_INV_MASK,

		buscfg->strobe_clk_pol);

	BIT_SET(val, ISPCCP2_CTRL_VP_CLK_POL_SHIFT,

		ISPCCP2_CTRL_VP_CLK_POL_MASK, buscfg->vp_clk_pol);

	isp_reg_writel(isp, val, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);



	val = isp_reg_readl(isp, OMAP3_ISP_IOMEM_CCP2, ISPCCP2_CTRL);

drivers/media/platform/omap3isp/ispreg.h

+4 −0
Original line number Diff line number Diff line
@@ -87,6 +87,8 @@ 
#define ISPCCP2_CTRL_PHY_SEL_MASK	0x1

#define ISPCCP2_CTRL_PHY_SEL_SHIFT	1

#define ISPCCP2_CTRL_IO_OUT_SEL		(1 << 2)

#define ISPCCP2_CTRL_IO_OUT_SEL_MASK	0x1

#define ISPCCP2_CTRL_IO_OUT_SEL_SHIFT	2

#define ISPCCP2_CTRL_MODE		(1 << 4)

#define ISPCCP2_CTRL_VP_CLK_FORCE_ON	(1 << 9)

#define ISPCCP2_CTRL_INV		(1 << 10)
@@ -94,6 +96,8 @@ 
#define ISPCCP2_CTRL_INV_SHIFT		10

#define ISPCCP2_CTRL_VP_ONLY_EN		(1 << 11)

#define ISPCCP2_CTRL_VP_CLK_POL		(1 << 12)

#define ISPCCP2_CTRL_VP_CLK_POL_MASK	0x1

#define ISPCCP2_CTRL_VP_CLK_POL_SHIFT	12

#define ISPCCP2_CTRL_VPCLK_DIV_SHIFT	15

#define ISPCCP2_CTRL_VPCLK_DIV_MASK	0x1ffff /* [31:15] */

#define ISPCCP2_CTRL_VP_OUT_CTRL_SHIFT	8 /* 3430 bits */