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Commit 376faf8a authored by Rodrigo Vivi's avatar Rodrigo Vivi
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drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F. 



Since when it got introduced with commit '555e38d2
("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
was wrong, because Port F bits are far from bits used
for A to E.

Since Port F is not used so far we don't need to propagate
Fixes back there.

v2: Reuse _SHIFT definition to avoid complicated duplication (DK).

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarDhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180129232223.766-5-rodrigo.vivi@intel.com
parent 8f942ed0

drivers/gpu/drm/i915/i915_reg.h

+6 −4
Original line number Diff line number Diff line
@@ -8759,10 +8759,12 @@ enum skl_power_gate { 
 * CNL Clocks

 */

#define DPCLKA_CFGCR0				_MMIO(0x6C200)

#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)+10))

#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << ((port)*2))

#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)

#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << ((port)*2))

#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \

						      (port)+10))

#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \

						(port)*2)

#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))

#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port))



/* CNL PLL */

#define DPLL0_ENABLE		0x46010