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Commit 3669ab61 authored by Arun Siluvery's avatar Arun Siluvery Committed by Daniel Vetter
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drm/i915/gen9: Add HDC_CHICKEN1 to HW whitelist 



Required for WaAllowUMDToModifyHDCChicken1:skl,bxt

This register is added to HW whitelist to support WA required for future
enabling of pre-emptive command execution, WA implementation will be in
userspace and it cannot program this register if it is not on HW whitelist.

v2: explain purpose of changes (Chris)

Reviewed-by: default avatarNick Hoath <nicholas.hoath@intel.com>
Signed-off-by: default avatarArun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453412634-29238-4-git-send-email-arun.siluvery@linux.intel.com


Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e0f3fa09

drivers/gpu/drm/i915/i915_reg.h

+2 −0
Original line number Diff line number Diff line
@@ -6045,6 +6045,8 @@ enum skl_disp_power_wells { 
#define  HDC_FORCE_NON_COHERENT			(1<<4)

#define  HDC_BARRIER_PERFORMANCE_DISABLE	(1<<10)



#define GEN8_HDC_CHICKEN1			_MMIO(0x7304)



/* GEN9 chicken */

#define SLICE_ECO_CHICKEN0			_MMIO(0x7308)

#define   PIXEL_MASK_CAMMING_DISABLE		(1 << 14)

drivers/gpu/drm/i915/intel_ringbuffer.c

+5 −0
Original line number Diff line number Diff line
@@ -986,6 +986,11 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring) 
	if (ret)

		return ret;



	/* WaAllowUMDToModifyHDCChicken1:skl,bxt */

	ret = wa_ring_whitelist_reg(ring, GEN8_HDC_CHICKEN1);

	if (ret)

		return ret;



	return 0;

}