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Commit 362cd03f authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k_hw: Add a HW callback to set diversity 



This patch adds a new callback to handle WLAN RX diversity for
AR9565.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 68f7586c

drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

+10 −0
Original line number Original line Diff line number Diff line
@@ -3629,6 +3629,16 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) 
		/* enable_lnadiv */

		/* enable_lnadiv */

		regval &= (~AR_PHY_ANT_DIV_LNADIV);

		regval &= (~AR_PHY_ANT_DIV_LNADIV);

		regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;

		regval |= ((value >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;



		if (AR_SREV_9565(ah)) {

			if (ah->shared_chain_lnadiv) {

				regval |= (1 << AR_PHY_ANT_SW_RX_PROT_S);

			} else {

				regval &= ~(1 << AR_PHY_ANT_DIV_LNADIV_S);

				regval &= ~(1 << AR_PHY_ANT_SW_RX_PROT_S);

			}

		}



		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);





		/*enable fast_div */

		/*enable fast_div */

drivers/net/wireless/ath/ath9k/ar9003_phy.c

+60 −0
Original line number Original line Diff line number Diff line
@@ -1325,6 +1325,65 @@ static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah, 
	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

}

}





static void ar9003_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,

						  bool enable)

{

	u8 ant_div_ctl1;

	u32 regval;



	if (!AR_SREV_9565(ah))

		return;



	ah->shared_chain_lnadiv = enable;

	ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);



	regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

	regval &= (~AR_ANT_DIV_CTRL_ALL);

	regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;

	regval &= ~AR_PHY_ANT_DIV_LNADIV;

	regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;



	if (enable)

		regval |= AR_ANT_DIV_ENABLE;



	REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);



	regval = REG_READ(ah, AR_PHY_CCK_DETECT);

	regval &= ~AR_FAST_DIV_ENABLE;

	regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;



	if (enable)

		regval |= AR_FAST_DIV_ENABLE;



	REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);



	if (enable) {

		REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,

			    (1 << AR_PHY_ANT_SW_RX_PROT_S));

		if (IS_CHAN_2GHZ(ah->curchan))

			REG_SET_BIT(ah, AR_PHY_RESTART,

				    AR_PHY_RESTART_ENABLE_DIV_M2FLAG);

		REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,

			    AR_BTCOEX_WL_LNADIV_FORCE_ON);

	} else {

		REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL, AR_ANT_DIV_ENABLE);

		REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,

			    (1 << AR_PHY_ANT_SW_RX_PROT_S));

		REG_CLR_BIT(ah, AR_PHY_CCK_DETECT, AR_FAST_DIV_ENABLE);

		REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,

			    AR_BTCOEX_WL_LNADIV_FORCE_ON);



		regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);

		regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |

			AR_PHY_ANT_DIV_ALT_LNACONF |

			AR_PHY_ANT_DIV_MAIN_GAINTB |

			AR_PHY_ANT_DIV_ALT_GAINTB);

		regval |= (AR_PHY_ANT_DIV_LNA1 << AR_PHY_ANT_DIV_MAIN_LNACONF_S);

		regval |= (AR_PHY_ANT_DIV_LNA2 << AR_PHY_ANT_DIV_ALT_LNACONF_S);

		REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);

	}

}



static int ar9003_hw_fast_chan_change(struct ath_hw *ah,

static int ar9003_hw_fast_chan_change(struct ath_hw *ah,

				      struct ath9k_channel *chan,

				      struct ath9k_channel *chan,

				      u8 *ini_reloaded)

				      u8 *ini_reloaded)
@@ -1423,6 +1482,7 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah) 




	ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;

	ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;

	ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;

	ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;

	ops->antctrl_shared_chain_lnadiv = ar9003_hw_antctrl_shared_chain_lnadiv;





	ar9003_hw_set_nf_limits(ah);

	ar9003_hw_set_nf_limits(ah);

	ar9003_hw_set_radar_conf(ah);

	ar9003_hw_set_radar_conf(ah);

drivers/net/wireless/ath/ath9k/ar9003_phy.h

+24 −0
Original line number Original line Diff line number Diff line
@@ -282,6 +282,8 @@ 




#define AR_PHY_ANT_FAST_DIV_BIAS                0x00007e00

#define AR_PHY_ANT_FAST_DIV_BIAS                0x00007e00

#define AR_PHY_ANT_FAST_DIV_BIAS_S              9

#define AR_PHY_ANT_FAST_DIV_BIAS_S              9

#define AR_PHY_ANT_SW_RX_PROT                   0x00800000

#define AR_PHY_ANT_SW_RX_PROT_S                 23

#define AR_PHY_ANT_DIV_LNADIV                   0x01000000

#define AR_PHY_ANT_DIV_LNADIV                   0x01000000

#define AR_PHY_ANT_DIV_LNADIV_S                 24

#define AR_PHY_ANT_DIV_LNADIV_S                 24

#define AR_PHY_ANT_DIV_ALT_LNACONF              0x06000000

#define AR_PHY_ANT_DIV_ALT_LNACONF              0x06000000
@@ -422,6 +424,8 @@ 
#define AR_PHY_FIND_SIG_RELSTEP        0x1f

#define AR_PHY_FIND_SIG_RELSTEP        0x1f

#define AR_PHY_FIND_SIG_RELSTEP_S         0

#define AR_PHY_FIND_SIG_RELSTEP_S         0

#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT  5

#define AR_PHY_FIND_SIG_RELSTEP_SIGN_BIT  5

#define AR_PHY_RESTART_ENABLE_DIV_M2FLAG 0x00200000

#define AR_PHY_RESTART_ENABLE_DIV_M2FLAG_S 21

#define AR_PHY_RESTART_DIV_GC   0x001C0000

#define AR_PHY_RESTART_DIV_GC   0x001C0000

#define AR_PHY_RESTART_DIV_GC_S 18

#define AR_PHY_RESTART_DIV_GC_S 18

#define AR_PHY_RESTART_ENA      0x01

#define AR_PHY_RESTART_ENA      0x01
@@ -1261,4 +1265,24 @@ 
#define AR_PHY_CL_TAB_CL_GAIN_MOD		0x1f

#define AR_PHY_CL_TAB_CL_GAIN_MOD		0x1f

#define AR_PHY_CL_TAB_CL_GAIN_MOD_S		0

#define AR_PHY_CL_TAB_CL_GAIN_MOD_S		0





#define AR_BTCOEX_WL_LNADIV                                0x1a64

#define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD               0x00003FFF

#define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S             0

#define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY           0x00004000

#define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY_S         14

#define AR_BTCOEX_WL_LNADIV_FORCE_ON                       0x00008000

#define AR_BTCOEX_WL_LNADIV_FORCE_ON_S                     15

#define AR_BTCOEX_WL_LNADIV_MODE_OPTION                    0x00030000

#define AR_BTCOEX_WL_LNADIV_MODE_OPTION_S                  16

#define AR_BTCOEX_WL_LNADIV_MODE                           0x007c0000

#define AR_BTCOEX_WL_LNADIV_MODE_S                         18

#define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ    0x00800000

#define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ_S  23

#define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE       0x01000000

#define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE_S     24

#define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT   0x02000000

#define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT_S 25

#define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD          0xFC000000

#define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD_S        26



#endif  /* AR9003_PHY_H */
 
#endif  /* AR9003_PHY_H */

drivers/net/wireless/ath/ath9k/hw-ops.h

+7 −0
Original line number Original line Diff line number Diff line
@@ -78,6 +78,13 @@ static inline void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah, 
	ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf);

	ath9k_hw_ops(ah)->antdiv_comb_conf_set(ah, antconf);

}

}





static inline void ath9k_hw_antctrl_shared_chain_lnadiv(struct ath_hw *ah,

							bool enable)

{

	if (ath9k_hw_ops(ah)->antctrl_shared_chain_lnadiv)

		ath9k_hw_ops(ah)->antctrl_shared_chain_lnadiv(ah, enable);

}



/* Private hardware call ops */

/* Private hardware call ops */





/* PHY ops */

/* PHY ops */

drivers/net/wireless/ath/ath9k/hw.c

+4 −0
Original line number Original line Diff line number Diff line
@@ -24,6 +24,7 @@ 
#include "rc.h"

#include "rc.h"

#include "ar9003_mac.h"

#include "ar9003_mac.h"

#include "ar9003_mci.h"

#include "ar9003_mci.h"

#include "ar9003_phy.h"

#include "debug.h"

#include "debug.h"

#include "ath9k.h"

#include "ath9k.h"
@@ -2025,6 +2026,9 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan, 




	ath9k_hw_apply_gpio_override(ah);

	ath9k_hw_apply_gpio_override(ah);





	if (AR_SREV_9565(ah) && ah->shared_chain_lnadiv)

		REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);



	return 0;

	return 0;

}

}

EXPORT_SYMBOL(ath9k_hw_reset);

EXPORT_SYMBOL(ath9k_hw_reset);