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Commit 362b334b authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
Browse files

ARM: dts: r8a7791: Convert to new CPG/MSSR bindings 



Convert the R-Car M2-W SoC from the old "Renesas R-Car Gen2 Clock Pulse
Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop
(MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse
Generator / Module Standby and Software Reset" DT bindings.

This simplifies the DTS files, and allows to add support for reset
control later.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent a7b8f48d

arch/arm/boot/dts/r8a7791-koelsch.dts

+1 −3
Original line number Diff line number Diff line
@@ -330,9 +330,7 @@ 
	pinctrl-names = "default";

	status = "okay";



	clocks = <&mstp7_clks R8A7791_CLK_DU0>,

		 <&mstp7_clks R8A7791_CLK_DU1>,

		 <&mstp7_clks R8A7791_CLK_LVDS0>,

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,

		 <&x13_clk>, <&x2_clk>;

	clock-names = "du.0", "du.1", "lvds.0",

		      "dclkin.0", "dclkin.1";

arch/arm/boot/dts/r8a7791-porter.dts

+1 −3
Original line number Diff line number Diff line
@@ -419,9 +419,7 @@ 
	pinctrl-names = "default";

	status = "okay";



	clocks = <&mstp7_clks R8A7791_CLK_DU0>,

		 <&mstp7_clks R8A7791_CLK_DU1>,

		 <&mstp7_clks R8A7791_CLK_LVDS0>,

	clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,

		 <&x3_clk>, <&x16_clk>;

	clock-names = "du.0", "du.1", "lvds.0",

		      "dclkin.0", "dclkin.1";

arch/arm/boot/dts/r8a7791.dtsi

+102 −455

File changed.

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