Loading include/dt-bindings/clock/rk3228-cru.h +1 −0 Original line number Original line Diff line number Diff line Loading @@ -49,6 +49,7 @@ #define SCLK_EMMC_DRV 117 #define SCLK_EMMC_DRV 117 #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 #define SCLK_SDIO_SAMPLE 119 #define SCLK_SDIO_SRC 120 #define SCLK_EMMC_SAMPLE 121 #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 #define SCLK_HDMI_HDCP 123 Loading include/dt-bindings/clock/rv1108-cru.h +2 −0 Original line number Original line Diff line number Diff line Loading @@ -110,6 +110,7 @@ #define ACLK_CIF2 207 #define ACLK_CIF2 207 #define ACLK_CIF3 208 #define ACLK_CIF3 208 #define ACLK_PERI 209 #define ACLK_PERI 209 #define ACLK_GMAC 210 /* pclk gates */ /* pclk gates */ #define PCLK_GPIO1 256 #define PCLK_GPIO1 256 Loading Loading @@ -141,6 +142,7 @@ #define PCLK_EFUSE0 282 #define PCLK_EFUSE0 282 #define PCLK_EFUSE1 283 #define PCLK_EFUSE1 283 #define PCLK_WDT 284 #define PCLK_WDT 284 #define PCLK_GMAC 285 /* hclk gates */ /* hclk gates */ #define HCLK_I2S0_8CH 320 #define HCLK_I2S0_8CH 320 Loading Loading
include/dt-bindings/clock/rk3228-cru.h +1 −0 Original line number Original line Diff line number Diff line Loading @@ -49,6 +49,7 @@ #define SCLK_EMMC_DRV 117 #define SCLK_EMMC_DRV 117 #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDMMC_SAMPLE 118 #define SCLK_SDIO_SAMPLE 119 #define SCLK_SDIO_SAMPLE 119 #define SCLK_SDIO_SRC 120 #define SCLK_EMMC_SAMPLE 121 #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 #define SCLK_HDMI_HDCP 123 Loading
include/dt-bindings/clock/rv1108-cru.h +2 −0 Original line number Original line Diff line number Diff line Loading @@ -110,6 +110,7 @@ #define ACLK_CIF2 207 #define ACLK_CIF2 207 #define ACLK_CIF3 208 #define ACLK_CIF3 208 #define ACLK_PERI 209 #define ACLK_PERI 209 #define ACLK_GMAC 210 /* pclk gates */ /* pclk gates */ #define PCLK_GPIO1 256 #define PCLK_GPIO1 256 Loading Loading @@ -141,6 +142,7 @@ #define PCLK_EFUSE0 282 #define PCLK_EFUSE0 282 #define PCLK_EFUSE1 283 #define PCLK_EFUSE1 283 #define PCLK_WDT 284 #define PCLK_WDT 284 #define PCLK_GMAC 285 /* hclk gates */ /* hclk gates */ #define HCLK_I2S0_8CH 320 #define HCLK_I2S0_8CH 320 Loading