bnx2x: Add support for BCM57711 HW (34f80b04) · Commits · e / devices / android_kernel_teracube_emerald

drivers/net/Kconfig

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -2600,6 +2600,7 @@ config BNX2X
	tristate "Broadcom NetXtremeII 10Gb support"		tristate "Broadcom NetXtremeII 10Gb support"
	depends on PCI		depends on PCI
	select ZLIB_INFLATE		select ZLIB_INFLATE
			select LIBCRC32C
	help		help
	This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards.		This driver supports Broadcom NetXtremeII 10 gigabit Ethernet cards.
	To compile this driver as a module, choose M here: the module		To compile this driver as a module, choose M here: the module

drivers/net/bnx2x.h

+437 −302

Original line number	Original line	Diff line number	Diff line
	@@ -14,6 +14,12 @@
	#ifndef BNX2X_H		#ifndef BNX2X_H
	#define BNX2X_H		#define BNX2X_H

			/* compilation time flags */

			/* define this to make the driver freeze on error to allow getting debug info
			* (you will need to reboot afterwards) */
			/* #define BNX2X_STOP_ON_ERROR */

	/* error/debug prints */		/* error/debug prints */

	#define DRV_MODULE_NAME "bnx2x"		#define DRV_MODULE_NAME "bnx2x"
	@@ -21,10 +27,10 @@

	/* for messages that are currently off */		/* for messages that are currently off */
	#define BNX2X_MSG_OFF 0		#define BNX2X_MSG_OFF 0
	#define BNX2X_MSG_MCP 0x10000 /* was: NETIF_MSG_HW */		#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */
	#define BNX2X_MSG_STATS 0x20000 /* was: NETIF_MSG_TIMER */		#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */
	#define NETIF_MSG_NVM 0x40000 /* was: NETIF_MSG_HW */		#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */
	#define NETIF_MSG_DMAE 0x80000 /* was: NETIF_MSG_HW */		#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */
	#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */		#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */
	#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */		#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */

	@@ -33,20 +39,21 @@
	/* regular debug print */		/* regular debug print */
	#define DP(__mask, __fmt, __args...) do { \		#define DP(__mask, __fmt, __args...) do { \
	if (bp->msglevel & (__mask)) \		if (bp->msglevel & (__mask)) \
	printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __FUNCTION__, \		printk(DP_LEVEL "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
	__LINE__, bp->dev?(bp->dev->name):"?", ##__args); \		bp->dev?(bp->dev->name):"?", ##__args); \
	} while (0)		} while (0)

	/* for errors (never masked) */		/* errors debug print */
	#define BNX2X_ERR(__fmt, __args...) do { \		#define BNX2X_DBG_ERR(__fmt, __args...) do { \
	printk(KERN_ERR "[%s:%d(%s)]" __fmt, __FUNCTION__, \		if (bp->msglevel & NETIF_MSG_PROBE) \
	__LINE__, bp->dev?(bp->dev->name):"?", ##__args); \		printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
			bp->dev?(bp->dev->name):"?", ##__args); \
	} while (0)		} while (0)

	/* for logging (never masked) */		/* for errors (never masked) */
	#define BNX2X_LOG(__fmt, __args...) do { \		#define BNX2X_ERR(__fmt, __args...) do { \
	printk(KERN_NOTICE "[%s:%d(%s)]" __fmt, __FUNCTION__, \		printk(KERN_ERR "[%s:%d(%s)]" __fmt, __func__, __LINE__, \
	__LINE__, bp->dev?(bp->dev->name):"?", ##__args); \		bp->dev?(bp->dev->name):"?", ##__args); \
	} while (0)		} while (0)

	/* before we have a dev->name use dev_info() */		/* before we have a dev->name use dev_info() */
	@@ -60,7 +67,7 @@
	#define bnx2x_panic() do { \		#define bnx2x_panic() do { \
	bp->panic = 1; \		bp->panic = 1; \
	BNX2X_ERR("driver assert\n"); \		BNX2X_ERR("driver assert\n"); \
	bnx2x_disable_int(bp); \		bnx2x_int_disable(bp); \
	bnx2x_panic_dump(bp); \		bnx2x_panic_dump(bp); \
	} while (0)		} while (0)
	#else		#else
	@@ -71,9 +78,14 @@
	#endif		#endif


	#define U64_LO(x) (((u64)x) & 0xffffffff)		#ifdef NETIF_F_HW_VLAN_TX
	#define U64_HI(x) (((u64)x) >> 32)		#define BCM_VLAN 1
	#define HILO_U64(hi, lo) (((u64)hi << 32) + lo)		#endif


			#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
			#define U64_HI(x) (u32)(((u64)(x)) >> 32)
			#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))


	#define REG_ADDR(bp, offset) (bp->regview + offset)		#define REG_ADDR(bp, offset) (bp->regview + offset)
	@@ -96,17 +108,17 @@
	memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \		memcpy(valp, bnx2x_sp(bp, wb_data[0]), len32 * 4); \
	} while (0)		} while (0)

	#define REG_WR_DMAE(bp, offset, val, len32) \		#define REG_WR_DMAE(bp, offset, valp, len32) \
	do { \		do { \
	memcpy(bnx2x_sp(bp, wb_data[0]), val, len32 * 4); \		memcpy(bnx2x_sp(bp, wb_data[0]), valp, len32 * 4); \
	bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \		bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
	offset, len32); \		offset, len32); \
	} while (0)		} while (0)

	#define SHMEM_RD(bp, type) \		#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
	REG_RD(bp, bp->shmem_base + offsetof(struct shmem_region, type))		offsetof(struct shmem_region, field))
	#define SHMEM_WR(bp, type, val) \		#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
	REG_WR(bp, bp->shmem_base + offsetof(struct shmem_region, type), val)		#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)

	#define NIG_WR(reg, val) REG_WR(bp, reg, val)		#define NIG_WR(reg, val) REG_WR(bp, reg, val)
	#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)		#define EMAC_WR(reg, val) REG_WR(bp, emac_base + reg, val)
	@@ -358,46 +370,7 @@ struct bnx2x_eth_stats {
	u32 number_of_bugs_found_in_stats_spec; /* just kidding */		u32 number_of_bugs_found_in_stats_spec; /* just kidding */
	};		};

	#define MAC_STX_NA 0xffffffff

	#ifdef BNX2X_MULTI
	#define MAX_CONTEXT 16
	#else
	#define MAX_CONTEXT 1
	#endif

	union cdu_context {
	struct eth_context eth;
	char pad[1024];
	};

	#define MAX_DMAE_C 5

	/* DMA memory not used in fastpath */
	struct bnx2x_slowpath {
	union cdu_context context[MAX_CONTEXT];
	struct eth_stats_query fw_stats;
	struct mac_configuration_cmd mac_config;
	struct mac_configuration_cmd mcast_config;

	/* used by dmae command executer */
	struct dmae_command dmae[MAX_DMAE_C];

	union mac_stats mac_stats;
	struct nig_stats nig;
	struct bnx2x_eth_stats eth_stats;

	u32 wb_comp;
	#define BNX2X_WB_COMP_VAL 0xe0d0d0ae
	u32 wb_data[4];
	};

	#define bnx2x_sp(bp, var) (&bp->slowpath->var)
	#define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)		#define bnx2x_sp_check(bp, var) ((bp->slowpath) ? (&bp->slowpath->var) : NULL)
	#define bnx2x_sp_mapping(bp, var) \
	(bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))


	struct sw_rx_bd {		struct sw_rx_bd {
	struct sk_buff *skb;		struct sk_buff *skb;
	DECLARE_PCI_UNMAP_ADDR(mapping)		DECLARE_PCI_UNMAP_ADDR(mapping)
	@@ -439,7 +412,14 @@ struct bnx2x_fastpath {
	#define BNX2X_FP_STATE_HALTING 0xb0000		#define BNX2X_FP_STATE_HALTING 0xb0000
	#define BNX2X_FP_STATE_HALTED 0xc0000		#define BNX2X_FP_STATE_HALTED 0xc0000

	int index;		u8 index; /* number in fp array */
			u8 cl_id; /* eth client id */
			u8 sb_id; /* status block number in HW */
			#define FP_IDX(fp) (fp->index)
			#define FP_CL_ID(fp) (fp->cl_id)
			#define BP_CL_ID(bp) (bp->fp[0].cl_id)
			#define FP_SB_ID(fp) (fp->sb_id)
			#define CNIC_SB_ID 0

	u16 tx_pkt_prod;		u16 tx_pkt_prod;
	u16 tx_pkt_cons;		u16 tx_pkt_cons;
	@@ -464,6 +444,157 @@ struct bnx2x_fastpath {
	};		};

	#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)		#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
			/* This is needed for determening of last_max */
			#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))

			/* stuff added to make the code fit 80Col */

			#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)

			#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG \| \
			ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG \| \
			ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)


			#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
			#define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
			#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS

			#define BNX2X_RX_SB_INDEX \
			(&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX])

			#define BNX2X_RX_SB_BD_INDEX \
			(&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])

			#define BNX2X_RX_SB_INDEX_NUM \
			(((U_SB_ETH_RX_CQ_INDEX << \
			USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
			USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) \| \
			((U_SB_ETH_RX_BD_INDEX << \
			USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
			USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))

			#define BNX2X_TX_SB_INDEX \
			(&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])

			/* common */

			struct bnx2x_common {

			u32 chip_id;
			/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
			#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)

			#define CHIP_NUM(bp) (bp->common.chip_id >> 16)
			#define CHIP_NUM_57710 0x164e
			#define CHIP_NUM_57711 0x164f
			#define CHIP_NUM_57711E 0x1650
			#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
			#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
			#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
			#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) \|\| \
			CHIP_IS_57711E(bp))
			#define IS_E1H_OFFSET CHIP_IS_E1H(bp)

			#define CHIP_REV(bp) (bp->common.chip_id & 0x0000f000)
			#define CHIP_REV_Ax 0x00000000
			/* assume maximum 5 revisions */
			#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
			/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
			#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
			!(CHIP_REV(bp) & 0x00001000))
			/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
			#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
			(CHIP_REV(bp) & 0x00001000))

			#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
			((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))

			#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
			#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)

			int flash_size;
			#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
			#define NVRAM_TIMEOUT_COUNT 30000
			#define NVRAM_PAGE_SIZE 256

			u32 shmem_base;

			u32 hw_config;
			u32 board;

			u32 bc_ver;

			char *name;
			};


			/* end of common */

			/* port */

			struct bnx2x_port {
			u32 pmf;

			u32 link_config;

			u32 supported;
			/* link settings - missing defines */
			#define SUPPORTED_2500baseX_Full (1 << 15)

			u32 advertising;
			/* link settings - missing defines */
			#define ADVERTISED_2500baseX_Full (1 << 15)

			u32 phy_addr;

			/* used to synchronize phy accesses */
			struct mutex phy_mutex;

			u32 port_stx;

			struct nig_stats old_nig_stats;
			};

			/* end of port */

			#define MAC_STX_NA 0xffffffff

			#ifdef BNX2X_MULTI
			#define MAX_CONTEXT 16
			#else
			#define MAX_CONTEXT 1
			#endif

			union cdu_context {
			struct eth_context eth;
			char pad[1024];
			};

			#define MAX_DMAE_C 6

			/* DMA memory not used in fastpath */
			struct bnx2x_slowpath {
			union cdu_context context[MAX_CONTEXT];
			struct eth_stats_query fw_stats;
			struct mac_configuration_cmd mac_config;
			struct mac_configuration_cmd mcast_config;

			/* used by dmae command executer */
			struct dmae_command dmae[MAX_DMAE_C];

			union mac_stats mac_stats;
			struct nig_stats nig;
			struct bnx2x_eth_stats eth_stats;

			u32 wb_comp;
			#define BNX2X_WB_COMP_VAL 0xe0d0d0ae
			u32 wb_data[4];
			};

			#define bnx2x_sp(bp, var) (&bp->slowpath->var)
			#define bnx2x_sp_mapping(bp, var) \
			(bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))


	/* attn group wiring */		/* attn group wiring */
	@@ -477,9 +608,10 @@ struct bnx2x {
	/* Fields used in the tx and intr/napi performance paths		/* Fields used in the tx and intr/napi performance paths
	* are grouped together in the beginning of the structure		* are grouped together in the beginning of the structure
	*/		*/
	struct bnx2x_fastpath *fp;		struct bnx2x_fastpath fp[MAX_CONTEXT];
	void __iomem *regview;		void __iomem *regview;
	void __iomem *doorbells;		void __iomem *doorbells;
			#define BNX2X_DB_SIZE (16*2048)

	struct net_device *dev;		struct net_device *dev;
	struct pci_dev *pdev;		struct pci_dev *pdev;
	@@ -506,8 +638,8 @@ struct bnx2x {
	#define DEF_SB_ID 16		#define DEF_SB_ID 16
	u16 def_c_idx;		u16 def_c_idx;
	u16 def_u_idx;		u16 def_u_idx;
	u16 def_t_idx;
	u16 def_x_idx;		u16 def_x_idx;
			u16 def_t_idx;
	u16 def_att_idx;		u16 def_att_idx;
	u32 attn_state;		u32 attn_state;
	struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];		struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
	@@ -522,6 +654,7 @@ struct bnx2x {
	struct eth_spe *spq_last_bd;		struct eth_spe *spq_last_bd;
	u16 *dsb_sp_prod;		u16 *dsb_sp_prod;
	u16 spq_left; /* serialize spq */		u16 spq_left; /* serialize spq */
			/* used to synchronize spq accesses */
	spinlock_t spq_lock;		spinlock_t spq_lock;

	/* Flag for marking that there is either		/* Flag for marking that there is either
	@@ -529,7 +662,7 @@ struct bnx2x {
	*/		*/
	u8 stat_pending;		u8 stat_pending;

	/* End of fields used in the performance code paths */		/* End of fileds used in the performance code paths */

	int panic;		int panic;
	int msglevel;		int msglevel;
	@@ -542,8 +675,17 @@ struct bnx2x {
	#define USING_DAC_FLAG 0x10		#define USING_DAC_FLAG 0x10
	#define USING_MSIX_FLAG 0x20		#define USING_MSIX_FLAG 0x20
	#define ASF_ENABLE_FLAG 0x40		#define ASF_ENABLE_FLAG 0x40
			#define NO_MCP_FLAG 0x100
	int port;		#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)

			int func;
			#define BP_PORT(bp) (bp->func % PORT_MAX)
			#define BP_FUNC(bp) (bp->func)
			#define BP_E1HVN(bp) (bp->func >> 1)
			#define BP_L_ID(bp) (BP_E1HVN(bp) << 2)
			/* assorted E1HVN */
			#define IS_E1HMF(bp) (bp->e1hmf != 0)
			#define BP_MAX_QUEUES(bp) (IS_E1HMF(bp) ? 4 : 16)

	int pm_cap;		int pm_cap;
	int pcie_cap;		int pcie_cap;
	@@ -555,76 +697,19 @@ struct bnx2x {
	int timer_interval;		int timer_interval;
	int current_interval;		int current_interval;

	u32 shmem_base;

	u32 chip_id;
	/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
	#define CHIP_ID(bp) (bp->chip_id & 0xfffffff0)

	#define CHIP_NUM(bp) (bp->chip_id >> 16)
	#define CHIP_NUM_57710 0x164e
	#define CHIP_NUM_57711 0x164f
	#define CHIP_NUM_57711E 0x1650
	#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
	#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
	#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
	#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) \|\| \
	CHIP_IS_57711E(bp))
	#define IS_E1H_OFFSET CHIP_IS_E1H(bp)

	#define CHIP_REV(bp) (bp->chip_id & 0x0000f000)
	#define CHIP_REV_Ax 0x00000000
	/* assume maximum 5 revisions */
	#define CHIP_REV_IS_SLOW(bp) (CHIP_REV(bp) > 0x00005000)
	/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
	#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
	!(CHIP_REV(bp) & 0x00001000))
	/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
	#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
	(CHIP_REV(bp) & 0x00001000))

	#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
	((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))

	#define CHIP_METAL(bp) (bp->chip_id & 0x00000ff0)
	#define CHIP_BOND_ID(bp) (bp->chip_id & 0x0000000f)

	u16 fw_seq;		u16 fw_seq;
	u16 fw_drv_pulse_wr_seq;		u16 fw_drv_pulse_wr_seq;
	u32 fw_mb;		u32 func_stx;

	u32 hw_config;
	u32 board;

	struct link_params link_params;		struct link_params link_params;

	struct link_vars link_vars;		struct link_vars link_vars;

	u32 link_config;		struct bnx2x_common common;
			struct bnx2x_port port;
	u32 supported;
	/* link settings - missing defines */
	#define SUPPORTED_2500baseT_Full (1 << 15)

	u32 phy_addr;

	/* used to synchronize phy accesses */
	struct mutex phy_mutex;

	u32 phy_id;

			u32 mf_config;
	u32 advertising;		u16 e1hov;
	/* link settings - missing defines */		u8 e1hmf;
	#define ADVERTISED_2500baseT_Full (1 << 15)


	u32 bc_ver;

	int flash_size;
	#define NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
	#define NVRAM_TIMEOUT_COUNT 30000
	#define NVRAM_PAGE_SIZE 256

	u8 wol;		u8 wol;

	@@ -641,6 +726,7 @@ struct bnx2x {
	u16 rx_ticks;		u16 rx_ticks;

	u32 stats_ticks;		u32 stats_ticks;
			u32 lin_cnt;

	int state;		int state;
	#define BNX2X_STATE_CLOSED 0x0		#define BNX2X_STATE_CLOSED 0x0
	@@ -650,7 +736,9 @@ struct bnx2x {
	#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000		#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
	#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000		#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
	#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000		#define BNX2X_STATE_CLOSING_WAIT4_UNLOAD 0x6000
	#define BNX2X_STATE_ERROR 0xF000		#define BNX2X_STATE_DISABLED 0xd000
			#define BNX2X_STATE_DIAG 0xe000
			#define BNX2X_STATE_ERROR 0xf000

	int num_queues;		int num_queues;

	@@ -742,8 +830,10 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);

	/* MC hsi */		/* MC hsi */
	#define RX_COPY_THRESH 92		#define RX_COPY_THRESH 92
	#define BCM_PAGE_BITS 12		#define BCM_PAGE_SHIFT 12
	#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)		#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
			#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
			#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)

	#define NUM_TX_RINGS 16		#define NUM_TX_RINGS 16
	#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))		#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_tx_bd))
	@@ -795,26 +885,11 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);


	/* must be used on a CID before placing it on a HW ring */		/* must be used on a CID before placing it on a HW ring */
	#define HW_CID(bp, x) (x \| (bp->port << 23))		#define HW_CID(bp, x) ((BP_PORT(bp) << 23) \| (BP_E1HVN(bp) << 17) \| x)

	#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))		#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
	#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)		#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)

	#define ATTN_NIG_FOR_FUNC (1L << 8)
	#define ATTN_SW_TIMER_4_FUNC (1L << 9)
	#define GPIO_2_FUNC (1L << 10)
	#define GPIO_3_FUNC (1L << 11)
	#define GPIO_4_FUNC (1L << 12)
	#define ATTN_GENERAL_ATTN_1 (1L << 13)
	#define ATTN_GENERAL_ATTN_2 (1L << 14)
	#define ATTN_GENERAL_ATTN_3 (1L << 15)
	#define ATTN_GENERAL_ATTN_4 (1L << 13)
	#define ATTN_GENERAL_ATTN_5 (1L << 14)
	#define ATTN_GENERAL_ATTN_6 (1L << 15)

	#define ATTN_HARD_WIRED_MASK 0xff00
	#define ATTENTION_ID 4


	#define BNX2X_BTR 3		#define BNX2X_BTR 3
	#define MAX_SPQ_PENDING 8		#define MAX_SPQ_PENDING 8
	@@ -831,6 +906,31 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
	DPM_TRIGER_TYPE); \		DPM_TRIGER_TYPE); \
	} while (0)		} while (0)

			static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
			int wait)
			{
			u32 val;

			do {
			val = REG_RD(bp, reg);
			if (val == expected)
			break;
			ms -= wait;
			msleep(wait);

			} while (ms > 0);

			return val;
			}


			/* load/unload mode */
			#define LOAD_NORMAL 0
			#define LOAD_OPEN 1
			#define LOAD_DIAG 2
			#define UNLOAD_NORMAL 0
			#define UNLOAD_CLOSE 1

	/* DMAE command defines */		/* DMAE command defines */
	#define DMAE_CMD_SRC_PCI 0		#define DMAE_CMD_SRC_PCI 0
	#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC		#define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
	@@ -877,22 +977,47 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);

	#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)		#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)

	/* stuff added to make the code fit 80Col */		/* must be used on a CID before placing it on a HW ring */

	#define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
	#define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
	#define TPA_TYPE(cqe) (cqe->fast_path_cqe.error_type_flags & \
	(TPA_TYPE_START \| TPA_TYPE_END))
	#define BNX2X_RX_SUM_OK(cqe) \		#define BNX2X_RX_SUM_OK(cqe) \
	(!(cqe->fast_path_cqe.status_flags & \		(!(cqe->fast_path_cqe.status_flags & \
	(ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG \| \		(ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG \| \
	ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))		ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)))

	#define BNX2X_RX_SUM_FIX(cqe) \		/* CMNG constants
	((le16_to_cpu(cqe->fast_path_cqe.pars_flags.flags) & \		derived from lab experiments, and not from system spec calculations !!! */
	PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \		#define DEF_MIN_RATE 100
	(1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))		/* resolution of the rate shaping timer - 100 usec */
			#define RS_PERIODIC_TIMEOUT_USEC 100
			/* resolution of fairness algorithm in usecs -
			coefficient for clauclating the actuall t fair */
			#define T_FAIR_COEF 10000000
			/* number of bytes in single QM arbitration cycle -
			coeffiecnt for calculating the fairness timer */
			#define QM_ARB_BYTES 40000
			#define FAIR_MEM 2


			#define ATTN_NIG_FOR_FUNC (1L << 8)
			#define ATTN_SW_TIMER_4_FUNC (1L << 9)
			#define GPIO_2_FUNC (1L << 10)
			#define GPIO_3_FUNC (1L << 11)
			#define GPIO_4_FUNC (1L << 12)
			#define ATTN_GENERAL_ATTN_1 (1L << 13)
			#define ATTN_GENERAL_ATTN_2 (1L << 14)
			#define ATTN_GENERAL_ATTN_3 (1L << 15)
			#define ATTN_GENERAL_ATTN_4 (1L << 13)
			#define ATTN_GENERAL_ATTN_5 (1L << 14)
			#define ATTN_GENERAL_ATTN_6 (1L << 15)

			#define ATTN_HARD_WIRED_MASK 0xff00
			#define ATTENTION_ID 4


			/* stuff added to make the code fit 80Col */

			#define BNX2X_PMF_LINK_ASSERT \
			GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))

	#define BNX2X_MC_ASSERT_BITS \		#define BNX2X_MC_ASSERT_BITS \
	(GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) \| \		(GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) \| \
	@@ -906,6 +1031,14 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
	#define BNX2X_DOORQ_ASSERT \		#define BNX2X_DOORQ_ASSERT \
	AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT		AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT

			#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
			#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) \| \
			GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) \| \
			GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) \| \
			GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) \| \
			GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) \| \
			GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))

	#define HW_INTERRUT_ASSERT_SET_0 \		#define HW_INTERRUT_ASSERT_SET_0 \
	(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT \| \		(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT \| \
	AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT \| \		AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT \| \
	@@ -954,11 +1087,6 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
	AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)		AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)


	#define ETH_RX_ERROR_FALGS (ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG \| \
	ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG \| \
	ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)


	#define MULTI_FLAGS \		#define MULTI_FLAGS \
	(TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY \| \		(TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY \| \
	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY \| \		TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY \| \
	@@ -969,27 +1097,34 @@ int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode);
	#define MULTI_MASK 0x7f		#define MULTI_MASK 0x7f


	#define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS		#define DEF_USB_FUNC_OFF (2 + 2*HC_USTORM_DEF_SB_NUM_INDICES)
	#define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS		#define DEF_CSB_FUNC_OFF (2 + 2*HC_CSTORM_DEF_SB_NUM_INDICES)
	#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH		#define DEF_XSB_FUNC_OFF (2 + 2*HC_XSTORM_DEF_SB_NUM_INDICES)
			#define DEF_TSB_FUNC_OFF (2 + 2*HC_TSTORM_DEF_SB_NUM_INDICES)

	#define BNX2X_RX_SB_INDEX \		#define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
	&fp->status_blk->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]

	#define BNX2X_TX_SB_INDEX \
	&fp->status_blk->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX]

	#define BNX2X_SP_DSB_INDEX \		#define BNX2X_SP_DSB_INDEX \
	&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]		(&bp->def_status_blk->c_def_status_block.index_values[C_DEF_SB_SP_INDEX])


	#define CAM_IS_INVALID(x) \		#define CAM_IS_INVALID(x) \
	(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)		(x.target_table_entry.flags == TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)

	#define CAM_INVALIDATE(x) \		#define CAM_INVALIDATE(x) \
	x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE		(x.target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)


			/* Number of u32 elements in MC hash array */
			#define MC_HASH_SIZE 8
			#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
			TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)


			#ifndef PXP2_REG_PXP2_INT_STS
			#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
			#endif

	/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */		/* MISC_REG_RESET_REG - this is here for the hsi to work don't touch */

	#endif /* bnx2x.h */		#endif /* bnx2x.h */