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Commit 345953cf authored by Kumar Gala's avatar Kumar Gala
Browse files

powerpc/mm: Fix Respect _PAGE_COHERENT on classic ppc32 SW TLB load machines 



Grant picked up the wrong version of "Respect _PAGE_COHERENT on classic
ppc32 SW" (commit a4bd6a93)

It was missing the code to actually deal with the fixup of
_PAGE_COHERENT based on the CPU feature.

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 9aac3975

arch/powerpc/kernel/head_32.S

+9 −0
Original line number Diff line number Diff line
@@ -513,6 +513,9 @@ InstructionTLBMiss: 
	rlwimi	r3,r3,32-1,31,31	/* _PAGE_USER -> PP lsb */

	ori	r1,r1,0xe04		/* clear out reserved bits */

	andc	r1,r3,r1		/* PP = user? (rw&dirty? 2: 3): 0 */

BEGIN_FTR_SECTION

	rlwinm	r1,r1,0,~_PAGE_COHERENT	/* clear M (coherence not required) */

END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)

	mtspr	SPRN_RPA,r1

	mfspr	r3,SPRN_IMISS

	tlbli	r3
@@ -587,6 +590,9 @@ DataLoadTLBMiss: 
	rlwimi	r3,r3,32-1,31,31	/* _PAGE_USER -> PP lsb */

	ori	r1,r1,0xe04		/* clear out reserved bits */

	andc	r1,r3,r1		/* PP = user? (rw&dirty? 2: 3): 0 */

BEGIN_FTR_SECTION

	rlwinm	r1,r1,0,~_PAGE_COHERENT	/* clear M (coherence not required) */

END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)

	mtspr	SPRN_RPA,r1

	mfspr	r3,SPRN_DMISS

	tlbld	r3
@@ -655,6 +661,9 @@ DataStoreTLBMiss: 
	rlwimi	r3,r3,32-1,30,30	/* _PAGE_USER -> PP msb */

	li	r1,0xe05		/* clear out reserved bits & PP lsb */

	andc	r1,r3,r1		/* PP = user? 2: 0 */

BEGIN_FTR_SECTION

	rlwinm	r1,r1,0,~_PAGE_COHERENT	/* clear M (coherence not required) */

END_FTR_SECTION_IFCLR(CPU_FTR_NEED_COHERENT)

	mtspr	SPRN_RPA,r1

	mfspr	r3,SPRN_DMISS

	tlbld	r3