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Commit 33057e16 authored by Sricharan R's avatar Sricharan R Committed by Andy Gross
Browse files

ARM: dts: ipq8074: Add pcie nodes 



The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.

Reviewed-by: default avatarAbhishek Sahu <absahu@codeaurora.org>
Acked-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarSricharan R <sricharan@codeaurora.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 22592a22

arch/arm64/boot/dts/qcom/ipq8074.dtsi

+156 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ 
		ranges = <0 0 0 0xffffffff>;

		compatible = "simple-bus";



		pinctrl@1000000 {

		tlmm: pinctrl@1000000 {

			compatible = "qcom,ipq8074-pinctrl";

			reg = <0x1000000 0x300000>;

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -278,6 +278,161 @@ 
			pinctrl-names = "default";

			status = "disabled";

		};



		pcie_phy0: phy@86000 {

			compatible = "qcom,ipq8074-qmp-pcie-phy";

			reg = <0x86000 0x1000>;

			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE0_PIPE_CLK>;

			clock-names = "pipe_clk";

			clock-output-names = "pcie20_phy0_pipe_clk";



			resets = <&gcc GCC_PCIE0_PHY_BCR>,

				<&gcc GCC_PCIE0PHY_PHY_BCR>;

			reset-names = "phy",

				      "common";

			status = "disabled";

		};



		pcie0: pci@20000000 {

			compatible = "qcom,pcie-ipq8074";

			reg =  <0x20000000 0xf1d

				0x20000f20 0xa8

				0x80000 0x2000

				0x20100000 0x1000>;

			reg-names = "dbi", "elbi", "parf", "config";

			device_type = "pci";

			linux,pci-domain = <0>;

			bus-range = <0x00 0xff>;

			num-lanes = <1>;

			#address-cells = <3>;

			#size-cells = <2>;



			phys = <&pcie_phy0>;

			phy-names = "pciephy";



			ranges = <0x81000000 0 0x20200000 0x20200000

				  0 0x100000   /* downstream I/O */

				  0x82000000 0 0x20300000 0x20300000

				  0 0xd00000>; /* non-prefetchable memory */



			interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 75

					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

					<0 0 0 2 &intc 0 78

					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

					<0 0 0 3 &intc 0 79

					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

					<0 0 0 4 &intc 0 83

					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



			clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,

				 <&gcc GCC_PCIE0_AXI_M_CLK>,

				 <&gcc GCC_PCIE0_AXI_S_CLK>,

				 <&gcc GCC_PCIE0_AHB_CLK>,

				 <&gcc GCC_PCIE0_AUX_CLK>;



			clock-names = "iface",

				      "axi_m",

				      "axi_s",

				      "ahb",

				      "aux";

			resets = <&gcc GCC_PCIE0_PIPE_ARES>,

				 <&gcc GCC_PCIE0_SLEEP_ARES>,

				 <&gcc GCC_PCIE0_CORE_STICKY_ARES>,

				 <&gcc GCC_PCIE0_AXI_MASTER_ARES>,

				 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,

				 <&gcc GCC_PCIE0_AHB_ARES>,

				 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;

			reset-names = "pipe",

				      "sleep",

				      "sticky",

				      "axi_m",

				      "axi_s",

				      "ahb",

				      "axi_m_sticky";

			status = "disabled";

		};



		pcie_phy1: phy@8e000 {

			compatible = "qcom,ipq8074-qmp-pcie-phy";

			reg = <0x8e000 0x1000>;

			#phy-cells = <0>;

			clocks = <&gcc GCC_PCIE1_PIPE_CLK>;

			clock-names = "pipe_clk";

			clock-output-names = "pcie20_phy1_pipe_clk";



			resets = <&gcc GCC_PCIE1_PHY_BCR>,

				<&gcc GCC_PCIE1PHY_PHY_BCR>;

			reset-names = "phy",

				      "common";

			status = "disabled";

		};



		pcie1: pci@10000000 {

			compatible = "qcom,pcie-ipq8074";

			reg =  <0x10000000 0xf1d

				0x10000f20 0xa8

				0x88000 0x2000

				0x10100000 0x1000>;

			reg-names = "dbi", "elbi", "parf", "config";

			device_type = "pci";

			linux,pci-domain = <1>;

			bus-range = <0x00 0xff>;

			num-lanes = <1>;

			#address-cells = <3>;

			#size-cells = <2>;



			phys = <&pcie_phy1>;

			phy-names = "pciephy";



			ranges = <0x81000000 0 0x10200000 0x10200000

				  0 0x100000   /* downstream I/O */

				  0x82000000 0 0x10300000 0x10300000

				  0 0xd00000>; /* non-prefetchable memory */



			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

			interrupt-names = "msi";

			#interrupt-cells = <1>;

			interrupt-map-mask = <0 0 0 0x7>;

			interrupt-map = <0 0 0 1 &intc 0 142

					 IRQ_TYPE_LEVEL_HIGH>, /* int_a */

					<0 0 0 2 &intc 0 143

					 IRQ_TYPE_LEVEL_HIGH>, /* int_b */

					<0 0 0 3 &intc 0 144

					 IRQ_TYPE_LEVEL_HIGH>, /* int_c */

					<0 0 0 4 &intc 0 145

					 IRQ_TYPE_LEVEL_HIGH>; /* int_d */



			clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,

				 <&gcc GCC_PCIE1_AXI_M_CLK>,

				 <&gcc GCC_PCIE1_AXI_S_CLK>,

				 <&gcc GCC_PCIE1_AHB_CLK>,

				 <&gcc GCC_PCIE1_AUX_CLK>;

			clock-names = "iface",

				      "axi_m",

				      "axi_s",

				      "ahb",

				      "aux";

			resets = <&gcc GCC_PCIE1_PIPE_ARES>,

				 <&gcc GCC_PCIE1_SLEEP_ARES>,

				 <&gcc GCC_PCIE1_CORE_STICKY_ARES>,

				 <&gcc GCC_PCIE1_AXI_MASTER_ARES>,

				 <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,

				 <&gcc GCC_PCIE1_AHB_ARES>,

				 <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;

			reset-names = "pipe",

				      "sleep",

				      "sticky",

				      "axi_m",

				      "axi_s",

				      "ahb",

				      "axi_m_sticky";

			status = "disabled";

		};

	};



	cpus {