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Commit 32ea06b6 authored by Ville Syrjälä's avatar Ville Syrjälä
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drm/i915: Don't set cursor pipe select bits on g4x+ 



G4x cursor control registers still allow us to write to the pipe select
bits even though cursors are supposed to be fixed to a specific pipe.
Bspec tells us that we should only ever write 0 to these bits. Let's
follow that recommendation. On ilk+ the bits become hardwired to 0.

Also looks like ICL repurposes these bits for some other use, so
we had better stop setting them to bogus values there.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180130203807.13721-1-ville.syrjala@linux.intel.com


Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
parent aa81e2c3

drivers/gpu/drm/i915/intel_display.c

+2 −1
Original line number Diff line number Diff line
@@ -9540,6 +9540,7 @@ static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, 
	if (HAS_DDI(dev_priv))

		cntl |= CURSOR_PIPE_CSC_ENABLE;



	if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))

		cntl |= MCURSOR_PIPE_SELECT(crtc->pipe);



	switch (plane_state->base.crtc_w) {