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Commit 32aa77a4 authored by Alexander Duyck's avatar Alexander Duyck Committed by Jeff Kirsher
Browse files

ixgbe: change vector numbering so that queues end up on correct CPUs 



This changes the numbering scheme slightly. Previously the ordering was
coming out like this:
Rx-2
Rx-1
Rx-0
TxRx-0
Which would drop two queues on CPU 0. This change makes it so that the
ordering is like this:
Rx-3
Rx-2
Rx-1
TxRx-0
This means that each CPU will have it's own Rx queue, and only CPU 0 will
have the Tx queue.

Signed-off-by: default avatarAlexander Duyck <alexander.h.duyck@intel.com>
Tested-by: default avatarRoss Brattain <ross.b.brattain@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent b953799e

drivers/net/ixgbe/ixgbe_main.c

+4 −2
Original line number Diff line number Diff line
@@ -2182,9 +2182,11 @@ static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter) 
		} else if (handler == &ixgbe_msix_clean_tx) {

			sprintf(adapter->name[vector], "%s-%s-%d",

				netdev->name, "tx", ti++);

		} else

		} else {

			sprintf(adapter->name[vector], "%s-%s-%d",

				netdev->name, "TxRx", vector);

				netdev->name, "TxRx", ri++);

			ti++;

		}



		err = request_irq(adapter->msix_entries[vector].vector,

				  handler, 0, adapter->name[vector],