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Commit 30bda41a authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm: Drop WIMG in favour of new constants 



PowerISA 3.0 introduces two pte bits with the below meaning for radix:
  00 -> Normal Memory
  01 -> Strong Access Order (SAO)
  10 -> Non idempotent I/O (Cache inhibited and guarded)
  11 -> Tolerant I/O (Cache inhibited)

We drop the existing WIMG bits in the Linux page table in favour of the
above constants. We loose _PAGE_WRITETHRU with this conversion. We only
use writethru via pgprot_cached_wthru() which is used by
fbdev/controlfb.c which is Apple control display and also PPC32.

With respect to _PAGE_COHERENCE, we have been marking hpte always
coherent for some time now. htab_convert_pte_flags() always added
HPTE_R_M.

NOTE: KVM changes need closer review.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 72176dd0

arch/powerpc/include/asm/book3s/64/hash.h

+31 −39
Original line number Diff line number Diff line
@@ -21,11 +21,9 @@ 
#define _PAGE_RW		(_PAGE_READ | _PAGE_WRITE)

#define _PAGE_RWX		(_PAGE_READ | _PAGE_WRITE | _PAGE_EXEC)

#define _PAGE_PRIVILEGED	0x00008 /* kernel access only */

#define _PAGE_GUARDED		0x00010 /* G: guarded (side-effect) page */

/* M (memory coherence) is always set in the HPTE, so we don't need it here */

#define _PAGE_COHERENT		0x0

#define _PAGE_NO_CACHE		0x00020 /* I: cache inhibit */

#define _PAGE_WRITETHRU		0x00040 /* W: cache write-through */

#define _PAGE_SAO		0x00010 /* Strong access order */

#define _PAGE_NON_IDEMPOTENT	0x00020 /* non idempotent memory */

#define _PAGE_TOLERANT		0x00030 /* tolerant memory, cache inhibited */

#define _PAGE_DIRTY		0x00080 /* C: page changed */

#define _PAGE_ACCESSED		0x00100 /* R: page referenced */

#define _PAGE_SPECIAL		0x00400 /* software: special page */
@@ -43,7 +41,12 @@ 
#define _PAGE_HASHPTE		(1ul << 61)	/* PTE has associated HPTE */

#define _PAGE_PTE		(1ul << 62)	/* distinguishes PTEs from pointers */

#define _PAGE_PRESENT		(1ul << 63)	/* pte contains a translation */



/*

 * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE

 * Instead of fixing all of them, add an alternate define which

 * maps CI pte mapping.

 */

#define _PAGE_NO_CACHE		_PAGE_TOLERANT

/*

 * We need to differentiate between explicit huge page and THP huge

 * page, since THP huge page also need to track real subpage details
@@ -126,9 +129,6 @@ 
#define _PAGE_KERNEL_RWX	(_PAGE_PRIVILEGED | _PAGE_DIRTY | \

				 _PAGE_RW | _PAGE_EXEC)



/* Strong Access Ordering */

#define _PAGE_SAO		(_PAGE_WRITETHRU | _PAGE_NO_CACHE | _PAGE_COHERENT)



/* No page size encoding in the linux PTE */

#define _PAGE_PSIZE		0
@@ -147,10 +147,9 @@ 
/*

 * Mask of bits returned by pte_pgprot()

 */

#define PAGE_PROT_BITS	(_PAGE_GUARDED | _PAGE_COHERENT | _PAGE_NO_CACHE | \

			 _PAGE_WRITETHRU | _PAGE_4K_PFN | \

			 _PAGE_PRIVILEGED | _PAGE_ACCESSED |  _PAGE_READ |\

			 _PAGE_WRITE |  _PAGE_DIRTY | _PAGE_EXEC | \

#define PAGE_PROT_BITS  (_PAGE_SAO | _PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT | \

			 _PAGE_4K_PFN | _PAGE_PRIVILEGED | _PAGE_ACCESSED | \

			 _PAGE_READ | _PAGE_WRITE |  _PAGE_DIRTY | _PAGE_EXEC | \

			 _PAGE_SOFT_DIRTY)

/*

 * We define 2 sets of base prot bits, one for basic pages (ie,
@@ -159,7 +158,7 @@ 
 * the processor might need it for DMA coherency.

 */

#define _PAGE_BASE_NC	(_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_PSIZE)

#define _PAGE_BASE	(_PAGE_BASE_NC | _PAGE_COHERENT)

#define _PAGE_BASE	(_PAGE_BASE_NC)



/* Permission masks used to generate the __P and __S table,

 *
@@ -200,9 +199,9 @@ 
/* Permission masks used for kernel mappings */

#define PAGE_KERNEL	__pgprot(_PAGE_BASE | _PAGE_KERNEL_RW)

#define PAGE_KERNEL_NC	__pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \

				 _PAGE_NO_CACHE)

				 _PAGE_TOLERANT)

#define PAGE_KERNEL_NCG	__pgprot(_PAGE_BASE_NC | _PAGE_KERNEL_RW | \

				 _PAGE_NO_CACHE | _PAGE_GUARDED)

				 _PAGE_NON_IDEMPOTENT)

#define PAGE_KERNEL_X	__pgprot(_PAGE_BASE | _PAGE_KERNEL_RWX)

#define PAGE_KERNEL_RO	__pgprot(_PAGE_BASE | _PAGE_KERNEL_RO)

#define PAGE_KERNEL_ROX	__pgprot(_PAGE_BASE | _PAGE_KERNEL_ROX)
@@ -509,45 +508,26 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, 
	*ptep = pte;

}



/*

 * Macro to mark a page protection value as "uncacheable".

 */



#define _PAGE_CACHE_CTL	(_PAGE_COHERENT | _PAGE_GUARDED | _PAGE_NO_CACHE | \

			 _PAGE_WRITETHRU)

#define _PAGE_CACHE_CTL	(_PAGE_NON_IDEMPOTENT | _PAGE_TOLERANT)



#define pgprot_noncached pgprot_noncached

static inline pgprot_t pgprot_noncached(pgprot_t prot)

{

	return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |

			_PAGE_NO_CACHE | _PAGE_GUARDED);

			_PAGE_NON_IDEMPOTENT);

}



#define pgprot_noncached_wc pgprot_noncached_wc

static inline pgprot_t pgprot_noncached_wc(pgprot_t prot)

{

	return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |

			_PAGE_NO_CACHE);

			_PAGE_TOLERANT);

}



#define pgprot_cached pgprot_cached

static inline pgprot_t pgprot_cached(pgprot_t prot)

{

	return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |

			_PAGE_COHERENT);

}



#define pgprot_cached_wthru pgprot_cached_wthru

static inline pgprot_t pgprot_cached_wthru(pgprot_t prot)

{

	return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) |

			_PAGE_COHERENT | _PAGE_WRITETHRU);

}



#define pgprot_cached_noncoherent pgprot_cached_noncoherent

static inline pgprot_t pgprot_cached_noncoherent(pgprot_t prot)

{

	return __pgprot(pgprot_val(prot) & ~_PAGE_CACHE_CTL);

	return __pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL));

}



#define pgprot_writecombine pgprot_writecombine
@@ -555,6 +535,18 @@ static inline pgprot_t pgprot_writecombine(pgprot_t prot) 
{

	return pgprot_noncached_wc(prot);

}

/*

 * check a pte mapping have cache inhibited property

 */

static inline bool pte_ci(pte_t pte)

{

	unsigned long pte_v = pte_val(pte);



	if (((pte_v & _PAGE_CACHE_CTL) == _PAGE_TOLERANT) ||

	    ((pte_v & _PAGE_CACHE_CTL) == _PAGE_NON_IDEMPOTENT))

		return true;

	return false;

}



#ifdef CONFIG_TRANSPARENT_HUGEPAGE

extern void hpte_do_hugepage_flush(struct mm_struct *mm, unsigned long addr,

arch/powerpc/include/asm/kvm_book3s_64.h

+10 −17
Original line number Diff line number Diff line
@@ -276,19 +276,24 @@ static inline unsigned long hpte_make_readonly(unsigned long ptel) 
	return ptel;

}



static inline int hpte_cache_flags_ok(unsigned long ptel, unsigned long io_type)

static inline bool hpte_cache_flags_ok(unsigned long hptel, bool is_ci)

{

	unsigned int wimg = ptel & HPTE_R_WIMG;

	unsigned int wimg = hptel & HPTE_R_WIMG;



	/* Handle SAO */

	if (wimg == (HPTE_R_W | HPTE_R_I | HPTE_R_M) &&

	    cpu_has_feature(CPU_FTR_ARCH_206))

		wimg = HPTE_R_M;



	if (!io_type)

	if (!is_ci)

		return wimg == HPTE_R_M;



	return (wimg & (HPTE_R_W | HPTE_R_I)) == io_type;

	/*

	 * if host is mapped cache inhibited, make sure hptel also have

	 * cache inhibited.

	 */

	if (wimg & HPTE_R_W) /* FIXME!! is this ok for all guest. ? */

		return false;

	return !!(wimg & HPTE_R_I);

}



/*
@@ -325,18 +330,6 @@ static inline pte_t kvmppc_read_update_linux_pte(pte_t *ptep, int writing) 
	return new_pte;

}





/* Return HPTE cache control bits corresponding to Linux pte bits */

static inline unsigned long hpte_cache_bits(unsigned long pte_val)

{

#if _PAGE_NO_CACHE == HPTE_R_I && _PAGE_WRITETHRU == HPTE_R_W

	return pte_val & (HPTE_R_W | HPTE_R_I);

#else

	return ((pte_val & _PAGE_NO_CACHE) ? HPTE_R_I : 0) +

		((pte_val & _PAGE_WRITETHRU) ? HPTE_R_W : 0);

#endif

}



static inline bool hpte_read_permission(unsigned long pp, unsigned long key)

{

	if (key)

arch/powerpc/kvm/book3s_64_mmu_hv.c

+5 −6
Original line number Diff line number Diff line
@@ -447,7 +447,7 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu, 
	struct revmap_entry *rev;

	struct page *page, *pages[1];

	long index, ret, npages;

	unsigned long is_io;

	bool is_ci;

	unsigned int writing, write_ok;

	struct vm_area_struct *vma;

	unsigned long rcbits;
@@ -503,7 +503,7 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu, 
	smp_rmb();



	ret = -EFAULT;

	is_io = 0;

	is_ci = false;

	pfn = 0;

	page = NULL;

	pte_size = PAGE_SIZE;
@@ -521,7 +521,7 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu, 
			pfn = vma->vm_pgoff +

				((hva - vma->vm_start) >> PAGE_SHIFT);

			pte_size = psize;

			is_io = hpte_cache_bits(pgprot_val(vma->vm_page_prot));

			is_ci = pte_ci(__pte((pgprot_val(vma->vm_page_prot))));

			write_ok = vma->vm_flags & VM_WRITE;

		}

		up_read(&current->mm->mmap_sem);
@@ -558,10 +558,9 @@ int kvmppc_book3s_hv_page_fault(struct kvm_run *run, struct kvm_vcpu *vcpu, 
		goto out_put;



	/* Check WIMG vs. the actual page we're accessing */

	if (!hpte_cache_flags_ok(r, is_io)) {

		if (is_io)

	if (!hpte_cache_flags_ok(r, is_ci)) {

		if (is_ci)

			goto out_put;



		/*

		 * Allow guest to map emulated device memory as

		 * uncacheable, but actually make it cacheable.

arch/powerpc/kvm/book3s_hv_rm_mmu.c

+6 −6
Original line number Diff line number Diff line
@@ -175,7 +175,7 @@ long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags, 
	unsigned long g_ptel;

	struct kvm_memory_slot *memslot;

	unsigned hpage_shift;

	unsigned long is_io;

	bool is_ci;

	unsigned long *rmap;

	pte_t *ptep;

	unsigned int writing;
@@ -199,7 +199,7 @@ long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags, 
	gfn = gpa >> PAGE_SHIFT;

	memslot = __gfn_to_memslot(kvm_memslots_raw(kvm), gfn);

	pa = 0;

	is_io = ~0ul;

	is_ci = false;

	rmap = NULL;

	if (!(memslot && !(memslot->flags & KVM_MEMSLOT_INVALID))) {

		/* Emulated MMIO - mark this with key=31 */
@@ -250,7 +250,7 @@ long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags, 
			if (writing && !pte_write(pte))

				/* make the actual HPTE be read-only */

				ptel = hpte_make_readonly(ptel);

			is_io = hpte_cache_bits(pte_val(pte));

			is_ci = pte_ci(pte);

			pa = pte_pfn(pte) << PAGE_SHIFT;

			pa |= hva & (host_pte_size - 1);

			pa |= gpa & ~PAGE_MASK;
@@ -267,9 +267,9 @@ long kvmppc_do_h_enter(struct kvm *kvm, unsigned long flags, 
	else

		pteh |= HPTE_V_ABSENT;



	/* Check WIMG */

	if (is_io != ~0ul && !hpte_cache_flags_ok(ptel, is_io)) {

		if (is_io)

	/*If we had host pte mapping then  Check WIMG */

	if (ptep && !hpte_cache_flags_ok(ptel, is_ci)) {

		if (is_ci)

			return H_PARAMETER;

		/*

		 * Allow guest to map emulated device memory as

arch/powerpc/mm/hash64_64k.c

+1 −1
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access, 
		 * If so, bail out and refault as a 4k page

		 */

		if (!mmu_has_feature(MMU_FTR_CI_LARGE_PAGE) &&

		    unlikely(old_pte & _PAGE_NO_CACHE))

		    unlikely(pte_ci(pte)))

			return 0;

		/*

		 * Try to lock the PTE, add ACCESSED and DIRTY if it was