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Commit 2f896ac0 authored by Ulf Hansson's avatar Ulf Hansson Committed by Mike Turquette
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clk: ux500: Update sdmmc clock to 100MHz for u8500 



For u8500 and using 100MHz as the frequency also requires the ape opp 100
voltage, thus use the prcmu_opp_volt_scalable clock type.

Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarMike Turquette <mturquette@linaro.org>
parent b0ea0fc7

drivers/clk/ux500/u8500_clk.c

+3 −2
Original line number Diff line number Diff line
@@ -170,10 +170,11 @@ void u8500_clk_init(void) 
	clk_register_clkdev(clk, NULL, "mtu0");

	clk_register_clkdev(clk, NULL, "mtu1");



	clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT);

	clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,

					100000000,

					CLK_IS_ROOT|CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, NULL, "sdmmc");





	clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",

				PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);

	clk_register_clkdev(clk, "dsihs2", "mcde");