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Commit 2e726dc4 authored by Dave Airlie's avatar Dave Airlie
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Merge tag 'mediatek-drm-2016-05-09' of git://git.pengutronix.de/git/pza/linux into drm-next 

MT8173 DRM support

- device tree binding documentation for all MT8173 display
  subsystem components
- basic mediatek-drm driver for MT8173 with two optional,
  currently fixed output paths:
- DSI encoder support for DSI and (via bridge) eDP panels
- DPI encoder support for output to HDMI bridge
- necessary clock tree changes for the DPI->HDMI path
- export mtk-smi functions used by mediatek-drm

* tag 'mediatek-drm-2016-05-09' of git://git.pengutronix.de/git/pza/linux:
  clk: mediatek: remove hdmitx_dig_cts from TOP clocks
  clk: mediatek: Add hdmi_ref HDMI PHY PLL reference clock output
  clk: mediatek: make dpi0_sel propagate rate changes
  drm/mediatek: Add DPI sub driver
  drm/mediatek: Add DSI sub driver
  drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.
  dt-bindings: drm/mediatek: Add Mediatek display subsystem dts binding
  memory: mtk-smi: export mtk_smi_larb_get/put
parents bafb86f5 ac4b1280

Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt

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Mediatek display subsystem

==========================



The Mediatek display subsystem consists of various DISP function blocks in the

MMSYS register space. The connections between them can be configured by output

and input selectors in the MMSYS_CONFIG register space. Pixel clock and start

of frame signal are distributed to the other function blocks by a DISP_MUTEX

function block.



All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.

For a description of the MMSYS_CONFIG binding, see

Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.



DISP function blocks

====================



A display stream starts at a source function block that reads pixel data from

memory and ends with a sink function block that drives pixels on a display

interface, or writes pixels back to memory. All DISP function blocks have

their own register space, interrupt, and clock gate. The blocks that can

access memory additionally have to list the IOMMU and local arbiter they are

connected to.



For a description of the display interface sink function blocks, see

Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and

Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt.



Required properties (all function blocks):

- compatible: "mediatek,<chip>-disp-<function>", one of

	"mediatek,<chip>-disp-ovl"   - overlay (4 layers, blending, csc)

	"mediatek,<chip>-disp-rdma"  - read DMA / line buffer

	"mediatek,<chip>-disp-wdma"  - write DMA

	"mediatek,<chip>-disp-color" - color processor

	"mediatek,<chip>-disp-aal"   - adaptive ambient light controller

	"mediatek,<chip>-disp-gamma" - gamma correction

	"mediatek,<chip>-disp-merge" - merge streams from two RDMA sources

	"mediatek,<chip>-disp-split" - split stream to two encoders

	"mediatek,<chip>-disp-ufoe"  - data compression engine

	"mediatek,<chip>-dsi"        - DSI controller, see mediatek,dsi.txt

	"mediatek,<chip>-dpi"        - DPI controller, see mediatek,dpi.txt

	"mediatek,<chip>-disp-mutex" - display mutex

	"mediatek,<chip>-disp-od"    - overdrive

- reg: Physical base address and length of the function block register space

- interrupts: The interrupt signal from the function block (required, except for

  merge and split function blocks).

- clocks: device clocks

  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.

  For most function blocks this is just a single clock input. Only the DSI and

  DPI controller nodes have multiple clock inputs. These are documented in

  mediatek,dsi.txt and mediatek,dpi.txt, respectively.



Required properties (DMA function blocks):

- compatible: Should be one of

	"mediatek,<chip>-disp-ovl"

	"mediatek,<chip>-disp-rdma"

	"mediatek,<chip>-disp-wdma"

- larb: Should contain a phandle pointing to the local arbiter device as defined

  in Documentation/devicetree/bindings/soc/mediatek/mediatek,smi-larb.txt

- iommus: Should point to the respective IOMMU block with master port as

  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt

  for details.



Examples:



mmsys: clock-controller@14000000 {

	compatible = "mediatek,mt8173-mmsys", "syscon";

	reg = <0 0x14000000 0 0x1000>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	#clock-cells = <1>;

};



ovl0: ovl@1400c000 {

	compatible = "mediatek,mt8173-disp-ovl";

	reg = <0 0x1400c000 0 0x1000>;

	interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_OVL0>;

	iommus = <&iommu M4U_PORT_DISP_OVL0>;

	mediatek,larb = <&larb0>;

};



ovl1: ovl@1400d000 {

	compatible = "mediatek,mt8173-disp-ovl";

	reg = <0 0x1400d000 0 0x1000>;

	interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_OVL1>;

	iommus = <&iommu M4U_PORT_DISP_OVL1>;

	mediatek,larb = <&larb4>;

};



rdma0: rdma@1400e000 {

	compatible = "mediatek,mt8173-disp-rdma";

	reg = <0 0x1400e000 0 0x1000>;

	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_RDMA0>;

	iommus = <&iommu M4U_PORT_DISP_RDMA0>;

	mediatek,larb = <&larb0>;

};



rdma1: rdma@1400f000 {

	compatible = "mediatek,mt8173-disp-rdma";

	reg = <0 0x1400f000 0 0x1000>;

	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_RDMA1>;

	iommus = <&iommu M4U_PORT_DISP_RDMA1>;

	mediatek,larb = <&larb4>;

};



rdma2: rdma@14010000 {

	compatible = "mediatek,mt8173-disp-rdma";

	reg = <0 0x14010000 0 0x1000>;

	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_RDMA2>;

	iommus = <&iommu M4U_PORT_DISP_RDMA2>;

	mediatek,larb = <&larb4>;

};



wdma0: wdma@14011000 {

	compatible = "mediatek,mt8173-disp-wdma";

	reg = <0 0x14011000 0 0x1000>;

	interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_WDMA0>;

	iommus = <&iommu M4U_PORT_DISP_WDMA0>;

	mediatek,larb = <&larb0>;

};



wdma1: wdma@14012000 {

	compatible = "mediatek,mt8173-disp-wdma";

	reg = <0 0x14012000 0 0x1000>;

	interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_WDMA1>;

	iommus = <&iommu M4U_PORT_DISP_WDMA1>;

	mediatek,larb = <&larb4>;

};



color0: color@14013000 {

	compatible = "mediatek,mt8173-disp-color";

	reg = <0 0x14013000 0 0x1000>;

	interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_COLOR0>;

};



color1: color@14014000 {

	compatible = "mediatek,mt8173-disp-color";

	reg = <0 0x14014000 0 0x1000>;

	interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_COLOR1>;

};



aal@14015000 {

	compatible = "mediatek,mt8173-disp-aal";

	reg = <0 0x14015000 0 0x1000>;

	interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_AAL>;

};



gamma@14016000 {

	compatible = "mediatek,mt8173-disp-gamma";

	reg = <0 0x14016000 0 0x1000>;

	interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_GAMMA>;

};



ufoe@1401a000 {

	compatible = "mediatek,mt8173-disp-ufoe";

	reg = <0 0x1401a000 0 0x1000>;

	interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_UFOE>;

};



dsi0: dsi@1401b000 {

	/* See mediatek,dsi.txt for details */

};



dpi0: dpi@1401d000 {

	/* See mediatek,dpi.txt for details */

};



mutex: mutex@14020000 {

	compatible = "mediatek,mt8173-disp-mutex";

	reg = <0 0x14020000 0 0x1000>;

	interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_MUTEX_32K>;

};



od@14023000 {

	compatible = "mediatek,mt8173-disp-od";

	reg = <0 0x14023000 0 0x1000>;

	power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;

	clocks = <&mmsys CLK_MM_DISP_OD>;

};

Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.txt

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Mediatek DPI Device

===================



The Mediatek DPI function block is a sink of the display subsystem and

provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel

output bus.



Required properties:

- compatible: "mediatek,<chip>-dpi"

- reg: Physical base address and length of the controller's registers

- interrupts: The interrupt signal from the function block.

- clocks: device clocks

  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.

- clock-names: must contain "pixel", "engine", and "pll"

- port: Output port node with endpoint definitions as described in

  Documentation/devicetree/bindings/graph.txt. This port should be connected

  to the input port of an attached HDMI or LVDS encoder chip.



Example:



dpi0: dpi@1401d000 {

	compatible = "mediatek,mt8173-dpi";

	reg = <0 0x1401d000 0 0x1000>;

	interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;

	clocks = <&mmsys CLK_MM_DPI_PIXEL>,

		 <&mmsys CLK_MM_DPI_ENGINE>,

		 <&apmixedsys CLK_APMIXED_TVDPLL>;

	clock-names = "pixel", "engine", "pll";



	port {

		dpi0_out: endpoint {

			remote-endpoint = <&hdmi0_in>;

		};

	};

};

Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt

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Mediatek DSI Device

===================



The Mediatek DSI function block is a sink of the display subsystem and can

drive up to 4-lane MIPI DSI output. Two DSIs can be synchronized for dual-

channel output.



Required properties:

- compatible: "mediatek,<chip>-dsi"

- reg: Physical base address and length of the controller's registers

- interrupts: The interrupt signal from the function block.

- clocks: device clocks

  See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.

- clock-names: must contain "engine", "digital", and "hs"

- phys: phandle link to the MIPI D-PHY controller.

- phy-names: must contain "dphy"

- port: Output port node with endpoint definitions as described in

  Documentation/devicetree/bindings/graph.txt. This port should be connected

  to the input port of an attached DSI panel or DSI-to-eDP encoder chip.



MIPI TX Configuration Module

============================



The MIPI TX configuration module controls the MIPI D-PHY.



Required properties:

- compatible: "mediatek,<chip>-mipi-tx"

- reg: Physical base address and length of the controller's registers

- clocks: PLL reference clock

- clock-output-names: name of the output clock line to the DSI encoder

- #clock-cells: must be <0>;

- #phy-cells: must be <0>.



Example:



mipi_tx0: mipi-dphy@10215000 {

	compatible = "mediatek,mt8173-mipi-tx";

	reg = <0 0x10215000 0 0x1000>;

	clocks = <&clk26m>;

	clock-output-names = "mipi_tx0_pll";

	#clock-cells = <0>;

	#phy-cells = <0>;

};



dsi0: dsi@1401b000 {

	compatible = "mediatek,mt8173-dsi";

	reg = <0 0x1401b000 0 0x1000>;

	interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>;

	clocks = <&mmsys MM_DSI0_ENGINE>, <&mmsys MM_DSI0_DIGITAL>,

		 <&mipi_tx0>;

	clock-names = "engine", "digital", "hs";

	phys = <&mipi_tx0>;

	phy-names = "dphy";



	port {

		dsi0_out: endpoint {

			remote-endpoint = <&panel_in>;

		};

	};

};

drivers/clk/mediatek/clk-mt8173.c

+10 −2
Original line number Original line Diff line number Diff line
@@ -61,7 +61,6 @@ static const struct mtk_fixed_factor top_divs[] __initconst = { 
	FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),

	FACTOR(CLK_TOP_CLKRTC_INT, "clkrtc_int", "clk26m", 1, 793),

	FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),

	FACTOR(CLK_TOP_FPC, "fpc_ck", "clk26m", 1, 1),





	FACTOR(CLK_TOP_HDMITX_DIG_CTS, "hdmitx_dig_cts", "tvdpll_445p5m", 1, 3),

	FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),

	FACTOR(CLK_TOP_HDMITXPLL_D2, "hdmitxpll_d2", "hdmitx_dig_cts", 1, 2),

	FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),

	FACTOR(CLK_TOP_HDMITXPLL_D3, "hdmitxpll_d3", "hdmitx_dig_cts", 1, 3),
@@ -558,7 +557,11 @@ static const struct mtk_composite top_muxes[] __initconst = { 
	MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),

	MUX_GATE(CLK_TOP_ATB_SEL, "atb_sel", atb_parents, 0x0090, 16, 2, 23),

	MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),

	MUX_GATE(CLK_TOP_VENC_LT_SEL, "venclt_sel", venc_lt_parents, 0x0090, 24, 4, 31),

	/* CLK_CFG_6 */

	/* CLK_CFG_6 */

	MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7),

	/*

	 * The dpi0_sel clock should not propagate rate changes to its parent

	 * clock so the dpi driver can have full control over PLL and divider.

	 */

	MUX_GATE_FLAGS(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents, 0x00a0, 0, 3, 7, 0),

	MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),

	MUX_GATE(CLK_TOP_IRDA_SEL, "irda_sel", irda_parents, 0x00a0, 8, 2, 15),

	MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),

	MUX_GATE(CLK_TOP_CCI400_SEL, "cci400_sel", cci400_parents, 0x00a0, 16, 3, 23),

	MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),

	MUX_GATE(CLK_TOP_AUD_1_SEL, "aud_1_sel", aud_1_parents, 0x00a0, 24, 2, 31),
@@ -1091,6 +1094,11 @@ static void __init mtk_apmixedsys_init(struct device_node *node) 
		clk_data->clks[cku->id] = clk;

		clk_data->clks[cku->id] = clk;

	}

	}





	clk = clk_register_divider(NULL, "hdmi_ref", "tvdpll_594m", 0,

				   base + 0x40, 16, 3, CLK_DIVIDER_POWER_OF_TWO,

				   NULL);

	clk_data->clks[CLK_APMIXED_HDMI_REF] = clk;



	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)

	if (r)

		pr_err("%s(): could not register clock provider: %d\n",

		pr_err("%s(): could not register clock provider: %d\n",

drivers/clk/mediatek/clk-mtk.h

+13 −2
Original line number Original line Diff line number Diff line
@@ -83,7 +83,11 @@ struct mtk_composite { 
	signed char num_parents;

	signed char num_parents;

};

};





#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) {	\

/*

 * In case the rate change propagation to parent clocks is undesirable,

 * this macro allows to specify the clock flags manually.

 */

#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) {	\

		.id = _id,						\

		.id = _id,						\

		.name = _name,						\

		.name = _name,						\

		.mux_reg = _reg,					\

		.mux_reg = _reg,					\
@@ -94,9 +98,16 @@ struct mtk_composite { 
		.divider_shift = -1,					\

		.divider_shift = -1,					\

		.parent_names = _parents,				\

		.parent_names = _parents,				\

		.num_parents = ARRAY_SIZE(_parents),			\

		.num_parents = ARRAY_SIZE(_parents),			\

		.flags = CLK_SET_RATE_PARENT,				\

		.flags = _flags,					\

	}

	}





/*

 * Unless necessary, all MUX_GATE clocks propagate rate changes to their

 * parent clock by default.

 */

#define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate)	\

	MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT)



#define MUX(_id, _name, _parents, _reg, _shift, _width) {		\

#define MUX(_id, _name, _parents, _reg, _shift, _width) {		\

		.id = _id,						\

		.id = _id,						\

		.name = _name,						\

		.name = _name,						\