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Commit 2e5be528 authored by Stefan Agner's avatar Stefan Agner Committed by Stephen Boyd
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clk: imx6ull: use OSC clock during AXI rate change 



On i.MX6 ULL using PLL3 seems to cause a freeze when setting
the parent to IMX6UL_CLK_PLL3_USB_OTG. This only seems to appear
since commit 6f9575e5 ("clk: imx: Add CLK_IS_CRITICAL flag
for busy divider and busy mux"), probably because the clock is
now forced to be on.

Fixes: 6f9575e5("clk: imx: Add CLK_IS_CRITICAL flag for busy divider and busy mux")
Signed-off-by: default avatarStefan Agner <stefan@agner.ch>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent c964cfc6

drivers/clk/imx/clk-imx6ul.c

+1 −1
Original line number Diff line number Diff line
@@ -464,7 +464,7 @@ static void __init imx6ul_clocks_init(struct device_node *ccm_node) 
	clk_set_rate(clks[IMX6UL_CLK_AHB], 99000000);



	/* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */

	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_PLL3_USB_OTG]);

	clk_set_parent(clks[IMX6UL_CLK_PERIPH_CLK2_SEL], clks[IMX6UL_CLK_OSC]);

	clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_CLK2]);

	clk_set_parent(clks[IMX6UL_CLK_PERIPH_PRE], clks[IMX6UL_CLK_PLL2_BUS]);

	clk_set_parent(clks[IMX6UL_CLK_PERIPH], clks[IMX6UL_CLK_PERIPH_PRE]);