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Commit 2e2ba09e authored by Mike Marciniszyn's avatar Mike Marciniszyn Committed by Jason Gunthorpe
Browse files

IB/rdmavt, IB/hfi1: Create device dependent s_flags 



Move some s_flags defines out of rdmavt and into hfi1 because they are
hfi1 specific and therefore should remain in the driver instead of
bubbling up to rdmavt.

Document device specific ranges in rdmavt and remap
those in hfi1.

Reviewed-by: default avatarDennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: default avatarMike Marciniszyn <mike.marciniszyn@intel.com>
Signed-off-by: default avatarKaike Wan <kaike.wan@intel.com>
Signed-off-by: default avatarDennis Dalessandro <dennis.dalessandro@intel.com>
Signed-off-by: default avatarJason Gunthorpe <jgg@mellanox.com>
parent 32e3d970

drivers/infiniband/hw/hfi1/pio.c

+3 −3
Original line number Diff line number Diff line 
/*

 * Copyright(c) 2015-2017 Intel Corporation.

 * Copyright(c) 2015-2018 Intel Corporation.

 *

 * This file is provided under a dual BSD/GPLv2 license.  When using or

 * redistributing this file, you may do so under either license.
@@ -1618,11 +1618,11 @@ static void sc_piobufavail(struct send_context *sc) 
	/* Wake up the most starved one first */

	if (n)

		hfi1_qp_wakeup(qps[max_idx],

			       RVT_S_WAIT_PIO | RVT_S_WAIT_PIO_DRAIN);

			       RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);

	for (i = 0; i < n; i++)

		if (i != max_idx)

			hfi1_qp_wakeup(qps[i],

				       RVT_S_WAIT_PIO | RVT_S_WAIT_PIO_DRAIN);

				       RVT_S_WAIT_PIO | HFI1_S_WAIT_PIO_DRAIN);

}



/* translate a send credit update to a bit code of reasons */

drivers/infiniband/hw/hfi1/qp.c

+3 −3
Original line number Diff line number Diff line 
/*

 * Copyright(c) 2015 - 2017 Intel Corporation.

 * Copyright(c) 2015 - 2018 Intel Corporation.

 *

 * This file is provided under a dual BSD/GPLv2 license.  When using or

 * redistributing this file, you may do so under either license.
@@ -273,7 +273,7 @@ void hfi1_modify_qp(struct rvt_qp *qp, struct ib_qp_attr *attr, 
	if (attr_mask & IB_QP_PATH_MIG_STATE &&

	    attr->path_mig_state == IB_MIG_MIGRATED &&

	    qp->s_mig_state == IB_MIG_ARMED) {

		qp->s_flags |= RVT_S_AHG_CLEAR;

		qp->s_flags |= HFI1_S_AHG_CLEAR;

		priv->s_sc = ah_to_sc(ibqp->device, &qp->remote_ah_attr);

		priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc);

		priv->s_sendcontext = qp_to_send_context(qp, priv->s_sc);
@@ -717,7 +717,7 @@ void hfi1_migrate_qp(struct rvt_qp *qp) 
	qp->remote_ah_attr = qp->alt_ah_attr;

	qp->port_num = rdma_ah_get_port_num(&qp->alt_ah_attr);

	qp->s_pkey_index = qp->s_alt_pkey_index;

	qp->s_flags |= RVT_S_AHG_CLEAR;

	qp->s_flags |= HFI1_S_AHG_CLEAR;

	priv->s_sc = ah_to_sc(qp->ibqp.device, &qp->remote_ah_attr);

	priv->s_sde = qp_to_sdma_engine(qp, priv->s_sc);

	qp_set_16b(qp);

drivers/infiniband/hw/hfi1/qp.h

+22 −2
Original line number Diff line number Diff line 
#ifndef _QP_H

#define _QP_H

/*

 * Copyright(c) 2015 - 2017 Intel Corporation.

 * Copyright(c) 2015 - 2018 Intel Corporation.

 *

 * This file is provided under a dual BSD/GPLv2 license.  When using or

 * redistributing this file, you may do so under either license.
@@ -69,6 +69,26 @@ static inline int hfi1_send_ok(struct rvt_qp *qp) 
		 !(qp->s_flags & RVT_S_ANY_WAIT_SEND));

}



/*

 * Driver specific s_flags starting at bit 31 down to HFI1_S_MIN_BIT_MASK

 *

 * HFI1_S_AHG_VALID - ahg header valid on chip

 * HFI1_S_AHG_CLEAR - have send engine clear ahg state

 * HFI1_S_WAIT_PIO_DRAIN - qp waiting for PIOs to drain

 * HFI1_S_MIN_BIT_MASK - the lowest bit that can be used by hfi1

 */

#define HFI1_S_AHG_VALID         0x80000000

#define HFI1_S_AHG_CLEAR         0x40000000

#define HFI1_S_WAIT_PIO_DRAIN    0x20000000

#define HFI1_S_MIN_BIT_MASK      0x01000000



/*

 * overload wait defines

 */



#define HFI1_S_ANY_WAIT_IO (RVT_S_ANY_WAIT_IO | HFI1_S_WAIT_PIO_DRAIN)

#define HFI1_S_ANY_WAIT (HFI1_S_ANY_WAIT_IO | RVT_S_ANY_WAIT_SEND)



/*

 * free_ahg - clear ahg from QP

 */
@@ -77,7 +97,7 @@ static inline void clear_ahg(struct rvt_qp *qp) 
	struct hfi1_qp_priv *priv = qp->priv;



	priv->s_ahg->ahgcount = 0;

	qp->s_flags &= ~(RVT_S_AHG_VALID | RVT_S_AHG_CLEAR);

	qp->s_flags &= ~(HFI1_S_AHG_VALID | HFI1_S_AHG_CLEAR);

	if (priv->s_sde && qp->s_ahgidx >= 0)

		sdma_ahg_free(priv->s_sde, qp->s_ahgidx);

	qp->s_ahgidx = -1;

drivers/infiniband/hw/hfi1/rc.c

+3 −3
Original line number Diff line number Diff line 
/*

 * Copyright(c) 2015, 2016 Intel Corporation.

 * Copyright(c) 2015 - 2018 Intel Corporation.

 *

 * This file is provided under a dual BSD/GPLv2 license.  When using or

 * redistributing this file, you may do so under either license.
@@ -241,7 +241,7 @@ static int make_rc_ack(struct hfi1_ibdev *dev, struct rvt_qp *qp, 
	smp_wmb();

	qp->s_flags &= ~(RVT_S_RESP_PENDING

				| RVT_S_ACK_PENDING

				| RVT_S_AHG_VALID);

				| HFI1_S_AHG_VALID);

	return 0;

}
@@ -1024,7 +1024,7 @@ static void reset_psn(struct rvt_qp *qp, u32 psn) 
	if ((cmp_psn(qp->s_psn, qp->s_sending_hpsn) <= 0) &&

	    (cmp_psn(qp->s_sending_psn, qp->s_sending_hpsn) <= 0))

		qp->s_flags |= RVT_S_WAIT_PSN;

	qp->s_flags &= ~RVT_S_AHG_VALID;

	qp->s_flags &= ~HFI1_S_AHG_VALID;

}



/*

drivers/infiniband/hw/hfi1/ruc.c

+7 −7
Original line number Diff line number Diff line 
/*

 * Copyright(c) 2015 - 2017 Intel Corporation.

 * Copyright(c) 2015 - 2018 Intel Corporation.

 *

 * This file is provided under a dual BSD/GPLv2 license.  When using or

 * redistributing this file, you may do so under either license.
@@ -194,7 +194,7 @@ static void ruc_loopback(struct rvt_qp *sqp) 
	spin_lock_irqsave(&sqp->s_lock, flags);



	/* Return if we are already busy processing a work request. */

	if ((sqp->s_flags & (RVT_S_BUSY | RVT_S_ANY_WAIT)) ||

	if ((sqp->s_flags & (RVT_S_BUSY | HFI1_S_ANY_WAIT)) ||

	    !(ib_rvt_state_ops[sqp->state] & RVT_PROCESS_OR_FLUSH_SEND))

		goto unlock;
@@ -533,9 +533,9 @@ static inline void build_ahg(struct rvt_qp *qp, u32 npsn) 
{

	struct hfi1_qp_priv *priv = qp->priv;



	if (unlikely(qp->s_flags & RVT_S_AHG_CLEAR))

	if (unlikely(qp->s_flags & HFI1_S_AHG_CLEAR))

		clear_ahg(qp);

	if (!(qp->s_flags & RVT_S_AHG_VALID)) {

	if (!(qp->s_flags & HFI1_S_AHG_VALID)) {

		/* first middle that needs copy  */

		if (qp->s_ahgidx < 0)

			qp->s_ahgidx = sdma_ahg_alloc(priv->s_sde);
@@ -544,7 +544,7 @@ static inline void build_ahg(struct rvt_qp *qp, u32 npsn) 
			priv->s_ahg->tx_flags |= SDMA_TXREQ_F_AHG_COPY;

			/* save to protect a change in another thread */

			priv->s_ahg->ahgidx = qp->s_ahgidx;

			qp->s_flags |= RVT_S_AHG_VALID;

			qp->s_flags |= HFI1_S_AHG_VALID;

		}

	} else {

		/* subsequent middle after valid */
@@ -650,7 +650,7 @@ static inline void hfi1_make_ruc_header_16B(struct rvt_qp *qp, 
	if (middle)

		build_ahg(qp, bth2);

	else

		qp->s_flags &= ~RVT_S_AHG_VALID;

		qp->s_flags &= ~HFI1_S_AHG_VALID;



	bth0 |= pkey;

	bth0 |= extra_bytes << 20;
@@ -727,7 +727,7 @@ static inline void hfi1_make_ruc_header_9B(struct rvt_qp *qp, 
	if (middle)

		build_ahg(qp, bth2);

	else

		qp->s_flags &= ~RVT_S_AHG_VALID;

		qp->s_flags &= ~HFI1_S_AHG_VALID;



	bth0 |= pkey;

	bth0 |= extra_bytes << 20;