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Commit 2e219345 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Greg Kroah-Hartman
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coresight tmc: Detect support for scatter gather 



The SG unit in the TMC has been removed in Coresight SoC-600.
This is however advertised by DEVID:Bit 24 = 0b1. On the
previous generation, the bit is RES0, hence we can rely on the
DEVID to detect the support.

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 2884132a

drivers/hwtracing/coresight/coresight-tmc.c

+2 −0
Original line number Diff line number Diff line
@@ -306,6 +306,8 @@ static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata, 
	/* Set the unadvertised capabilities */

	tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);



	if (!(devid & TMC_DEVID_NOSCAT))

		tmc_etr_set_cap(drvdata, TMC_ETR_SG);

	/*

	 * ETR configuration uses a 40-bit AXI master in place of

	 * the embedded SRAM of ETB/ETF.

drivers/hwtracing/coresight/coresight-tmc.h

+5 −0
Original line number Diff line number Diff line
@@ -69,6 +69,8 @@ 
#define TMC_FFCR_STOP_ON_FLUSH	BIT(12)





#define TMC_DEVID_NOSCAT	BIT(24)



enum tmc_config_type {

	TMC_CONFIG_TYPE_ETB,

	TMC_CONFIG_TYPE_ETR,
@@ -88,6 +90,9 @@ enum tmc_mem_intf_width { 
	TMC_MEM_INTF_WIDTH_256BITS	= 8,

};



/* TMC ETR Capability bit definitions */

#define TMC_ETR_SG			(0x1U << 0)



/**

 * struct tmc_drvdata - specifics associated to an TMC component

 * @base:	memory mapped base address for this component.