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Commit 2e145a22 authored by Lucas Stach's avatar Lucas Stach
Browse files

drm/etnaviv: add flushing logic for MMUv2 



Flushing works differently on MMUv2, in that it's only necessary
to set a single bit in the control register to flush all translation
units. A semaphore stall then makes sure that the flush has propagated
properly.

Signed-off-by: default avatarLucas Stach <l.stach@pengutronix.de>
parent de08e8ef

drivers/gpu/drm/etnaviv/etnaviv_buffer.c

+23 −8
Original line number Original line Diff line number Diff line
@@ -276,8 +276,12 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event, 
		extra_dwords = 1;

		extra_dwords = 1;





		/* flush command */

		/* flush command */

		if (gpu->mmu->need_flush)

		if (gpu->mmu->need_flush) {

			if (gpu->mmu->version == ETNAVIV_IOMMU_V1)

				extra_dwords += 1;

				extra_dwords += 1;

			else

				extra_dwords += 3;

		}





		/* pipe switch commands */

		/* pipe switch commands */

		if (gpu->switch_context)

		if (gpu->switch_context)
@@ -287,12 +291,23 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, unsigned int event, 




		if (gpu->mmu->need_flush) {

		if (gpu->mmu->need_flush) {

			/* Add the MMU flush */

			/* Add the MMU flush */

			if (gpu->mmu->version == ETNAVIV_IOMMU_V1) {

				CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,

				CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_MMU,

					       VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |

					       VIVS_GL_FLUSH_MMU_FLUSH_FEMMU |

					       VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |

					       VIVS_GL_FLUSH_MMU_FLUSH_UNK1 |

					       VIVS_GL_FLUSH_MMU_FLUSH_UNK2 |

					       VIVS_GL_FLUSH_MMU_FLUSH_UNK2 |

					       VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |

					       VIVS_GL_FLUSH_MMU_FLUSH_PEMMU |

					       VIVS_GL_FLUSH_MMU_FLUSH_UNK4);

					       VIVS_GL_FLUSH_MMU_FLUSH_UNK4);

			} else {

				CMD_LOAD_STATE(buffer, VIVS_MMUv2_CONFIGURATION,

					VIVS_MMUv2_CONFIGURATION_MODE_MASK |

					VIVS_MMUv2_CONFIGURATION_ADDRESS_MASK |

					VIVS_MMUv2_CONFIGURATION_FLUSH_FLUSH);

				CMD_SEM(buffer, SYNC_RECIPIENT_FE,

					SYNC_RECIPIENT_PE);

				CMD_STALL(buffer, SYNC_RECIPIENT_FE,

					SYNC_RECIPIENT_PE);

			}





			gpu->mmu->need_flush = false;

			gpu->mmu->need_flush = false;

		}

		}