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Commit 2d2cf346 authored by Sucheta Chakraborty's avatar Sucheta Chakraborty Committed by David S. Miller
Browse files

netxen: fix ethtool register dump 



o Dump registers such as tx ring and rx ring counter, firmware state,
  niu regs, etc. which can be useful for debugging purpose.

Signed-off-by: default avatarSucheta Chakraborty <sucheta.chakraborty@qlogic.com>
Signed-off-by: default avatarAmit Kumar Salecha <amit.salecha@qlogic.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2585e7e5

drivers/net/netxen/netxen_nic_ethtool.c

+59 −111
Original line number Original line Diff line number Diff line
@@ -66,7 +66,7 @@ static const char netxen_nic_gstrings_test[][ETH_GSTRING_LEN] = { 




#define NETXEN_NIC_TEST_LEN	ARRAY_SIZE(netxen_nic_gstrings_test)

#define NETXEN_NIC_TEST_LEN	ARRAY_SIZE(netxen_nic_gstrings_test)





#define NETXEN_NIC_REGS_COUNT 42

#define NETXEN_NIC_REGS_COUNT 30

#define NETXEN_NIC_REGS_LEN (NETXEN_NIC_REGS_COUNT * sizeof(__le32))

#define NETXEN_NIC_REGS_LEN (NETXEN_NIC_REGS_COUNT * sizeof(__le32))

#define NETXEN_MAX_EEPROM_LEN   1024

#define NETXEN_MAX_EEPROM_LEN   1024
@@ -312,125 +312,73 @@ static int netxen_nic_get_regs_len(struct net_device *dev) 
	return NETXEN_NIC_REGS_LEN;

	return NETXEN_NIC_REGS_LEN;

}

}





struct netxen_niu_regs {

	__u32 reg[NETXEN_NIC_REGS_COUNT];

};



static struct netxen_niu_regs niu_registers[] = {

	{

	 /* GB Mode */

	 {

	  NETXEN_NIU_GB_SERDES_RESET,

	  NETXEN_NIU_GB0_MII_MODE,

	  NETXEN_NIU_GB1_MII_MODE,

	  NETXEN_NIU_GB2_MII_MODE,

	  NETXEN_NIU_GB3_MII_MODE,

	  NETXEN_NIU_GB0_GMII_MODE,

	  NETXEN_NIU_GB1_GMII_MODE,

	  NETXEN_NIU_GB2_GMII_MODE,

	  NETXEN_NIU_GB3_GMII_MODE,

	  NETXEN_NIU_REMOTE_LOOPBACK,

	  NETXEN_NIU_GB0_HALF_DUPLEX,

	  NETXEN_NIU_GB1_HALF_DUPLEX,

	  NETXEN_NIU_RESET_SYS_FIFOS,

	  NETXEN_NIU_GB_CRC_DROP,

	  NETXEN_NIU_GB_DROP_WRONGADDR,

	  NETXEN_NIU_TEST_MUX_CTL,



	  NETXEN_NIU_GB_MAC_CONFIG_0(0),

	  NETXEN_NIU_GB_MAC_CONFIG_1(0),

	  NETXEN_NIU_GB_HALF_DUPLEX_CTRL(0),

	  NETXEN_NIU_GB_MAX_FRAME_SIZE(0),

	  NETXEN_NIU_GB_TEST_REG(0),

	  NETXEN_NIU_GB_MII_MGMT_CONFIG(0),

	  NETXEN_NIU_GB_MII_MGMT_COMMAND(0),

	  NETXEN_NIU_GB_MII_MGMT_ADDR(0),

	  NETXEN_NIU_GB_MII_MGMT_CTRL(0),

	  NETXEN_NIU_GB_MII_MGMT_STATUS(0),

	  NETXEN_NIU_GB_MII_MGMT_INDICATE(0),

	  NETXEN_NIU_GB_INTERFACE_CTRL(0),

	  NETXEN_NIU_GB_INTERFACE_STATUS(0),

	  NETXEN_NIU_GB_STATION_ADDR_0(0),

	  NETXEN_NIU_GB_STATION_ADDR_1(0),

	  -1,

	  }

	 },

	{

	 /* XG Mode */

	 {

	  NETXEN_NIU_XG_SINGLE_TERM,

	  NETXEN_NIU_XG_DRIVE_HI,

	  NETXEN_NIU_XG_DRIVE_LO,

	  NETXEN_NIU_XG_DTX,

	  NETXEN_NIU_XG_DEQ,

	  NETXEN_NIU_XG_WORD_ALIGN,

	  NETXEN_NIU_XG_RESET,

	  NETXEN_NIU_XG_POWER_DOWN,

	  NETXEN_NIU_XG_RESET_PLL,

	  NETXEN_NIU_XG_SERDES_LOOPBACK,

	  NETXEN_NIU_XG_DO_BYTE_ALIGN,

	  NETXEN_NIU_XG_TX_ENABLE,

	  NETXEN_NIU_XG_RX_ENABLE,

	  NETXEN_NIU_XG_STATUS,

	  NETXEN_NIU_XG_PAUSE_THRESHOLD,

	  NETXEN_NIU_XGE_CONFIG_0,

	  NETXEN_NIU_XGE_CONFIG_1,

	  NETXEN_NIU_XGE_IPG,

	  NETXEN_NIU_XGE_STATION_ADDR_0_HI,

	  NETXEN_NIU_XGE_STATION_ADDR_0_1,

	  NETXEN_NIU_XGE_STATION_ADDR_1_LO,

	  NETXEN_NIU_XGE_STATUS,

	  NETXEN_NIU_XGE_MAX_FRAME_SIZE,

	  NETXEN_NIU_XGE_PAUSE_FRAME_VALUE,

	  NETXEN_NIU_XGE_TX_BYTE_CNT,

	  NETXEN_NIU_XGE_TX_FRAME_CNT,

	  NETXEN_NIU_XGE_RX_BYTE_CNT,

	  NETXEN_NIU_XGE_RX_FRAME_CNT,

	  NETXEN_NIU_XGE_AGGR_ERROR_CNT,

	  NETXEN_NIU_XGE_MULTICAST_FRAME_CNT,

	  NETXEN_NIU_XGE_UNICAST_FRAME_CNT,

	  NETXEN_NIU_XGE_CRC_ERROR_CNT,

	  NETXEN_NIU_XGE_OVERSIZE_FRAME_ERR,

	  NETXEN_NIU_XGE_UNDERSIZE_FRAME_ERR,

	  NETXEN_NIU_XGE_LOCAL_ERROR_CNT,

	  NETXEN_NIU_XGE_REMOTE_ERROR_CNT,

	  NETXEN_NIU_XGE_CONTROL_CHAR_CNT,

	  NETXEN_NIU_XGE_PAUSE_FRAME_CNT,

	  -1,

	  }

	 }

};



static void

static void

netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)

netxen_nic_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *p)

{

{

	struct netxen_adapter *adapter = netdev_priv(dev);

	struct netxen_adapter *adapter = netdev_priv(dev);

	__u32 mode, *regs_buff = p;

	struct netxen_recv_context *recv_ctx = &adapter->recv_ctx;

	int i, window;

	struct nx_host_sds_ring *sds_ring;

	u32 *regs_buff = p;

	int ring, i = 0;

	int port = adapter->physical_port;





	memset(p, 0, NETXEN_NIC_REGS_LEN);

	memset(p, 0, NETXEN_NIC_REGS_LEN);



	regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |

	regs->version = (1 << 24) | (adapter->ahw.revision_id << 16) |

	    (adapter->pdev)->device;

	    (adapter->pdev)->device;

	/* which mode */



	regs_buff[0] = NXRD32(adapter, NETXEN_NIU_MODE);

	if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)

	mode = regs_buff[0];

		return;





	/* Common registers to all the modes */

	regs_buff[i++] = NXRD32(adapter, CRB_CMDPEG_STATE);

	regs_buff[2] = NXRD32(adapter, NETXEN_NIU_STRAP_VALUE_SAVE_HIGHER);

	regs_buff[i++] = NXRD32(adapter, CRB_RCVPEG_STATE);

	/* GB/XGB Mode */

	regs_buff[i++] = NXRD32(adapter, CRB_FW_CAPABILITIES_1);

	mode = (mode / 2) - 1;

	regs_buff[i++] = NXRDIO(adapter, adapter->crb_int_state_reg);

	window = 0;

	regs_buff[i++] = NXRD32(adapter, NX_CRB_DEV_REF_COUNT);

	if (mode <= 1) {

	regs_buff[i++] = NXRD32(adapter, NX_CRB_DEV_STATE);

		for (i = 3; niu_registers[mode].reg[i - 3] != -1; i++) {

	regs_buff[i++] = NXRD32(adapter, NETXEN_PEG_ALIVE_COUNTER);

			/* GB: port specific registers */

	regs_buff[i++] = NXRD32(adapter, NETXEN_PEG_HALT_STATUS1);

			if (mode == 0 && i >= 19)

	regs_buff[i++] = NXRD32(adapter, NETXEN_PEG_HALT_STATUS2);

				window = adapter->physical_port *



					NETXEN_NIC_PORT_WINDOW;

	regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_0+0x3c);



	regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_1+0x3c);

			regs_buff[i] = NXRD32(adapter,

	regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_2+0x3c);

				niu_registers[mode].reg[i - 3] + window);

	regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_3+0x3c);



	if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {



		regs_buff[i++] = NXRD32(adapter, NETXEN_CRB_PEG_NET_4+0x3c);

		i += 2;



		regs_buff[i++] = NXRD32(adapter, CRB_XG_STATE_P3);

		regs_buff[i++] = le32_to_cpu(*(adapter->tx_ring->hw_consumer));



	} else {

		i++;



		regs_buff[i++] = NXRD32(adapter,

					NETXEN_NIU_XGE_CONFIG_0+(0x10000*port));

		regs_buff[i++] = NXRD32(adapter,

					NETXEN_NIU_XGE_CONFIG_1+(0x10000*port));



		regs_buff[i++] = NXRD32(adapter, CRB_XG_STATE);

		regs_buff[i++] = NXRDIO(adapter,

				 adapter->tx_ring->crb_cmd_consumer);

	}

	}





	regs_buff[i++] = NXRDIO(adapter, adapter->tx_ring->crb_cmd_producer);



	regs_buff[i++] = NXRDIO(adapter,

			 recv_ctx->rds_rings[0].crb_rcv_producer);

	regs_buff[i++] = NXRDIO(adapter,

			 recv_ctx->rds_rings[1].crb_rcv_producer);



	regs_buff[i++] = adapter->max_sds_rings;



	for (ring = 0; ring < adapter->max_sds_rings; ring++) {

		sds_ring = &(recv_ctx->sds_rings[ring]);

		regs_buff[i++] = NXRDIO(adapter,

					sds_ring->crb_sts_consumer);

	}

	}

}

}