Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2d0b10fc authored by Abhinav Kumar's avatar Abhinav Kumar Committed by Sean Paul
Browse files

drm/msm: higher values of pclk can exceed 32 bits when multiplied by a factor 



Make the pclk_rate u64 to accommodate higher pixel clock
rates.

Changes in v3:
- Converted pclk_rate to u32 (Archit)
- Rebase on dsi cleanup set in msm-next

Cc: Sibi Sankar <sibis@codeaurora.org>
Cc: Archit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarAbhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent bb676df1

drivers/gpu/drm/msm/dsi/dsi_host.c

+5 −2
Original line number Diff line number Diff line
@@ -702,6 +702,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) 
	u8 lanes = msm_host->lanes;

	u32 bpp = dsi_get_bpp(msm_host->format);

	u32 pclk_rate;

	u64 pclk_bpp;

	unsigned int esc_mhz, esc_div;

	unsigned long byte_mhz;
@@ -716,13 +717,15 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) 
	if (is_dual_dsi)

		pclk_rate /= 2;



	pclk_bpp = pclk_rate * bpp;

	if (lanes > 0) {

		msm_host->byte_clk_rate = (pclk_rate * bpp) / (8 * lanes);

		do_div(pclk_bpp, (8 * lanes));

	} else {

		pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);

		msm_host->byte_clk_rate = (pclk_rate * bpp) / 8;

		do_div(pclk_bpp, 8);

	}

	msm_host->pixel_clk_rate = pclk_rate;

	msm_host->byte_clk_rate = pclk_bpp;



	DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate,

				msm_host->byte_clk_rate);