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Commit 2c97fa22 authored by Sean Wang's avatar Sean Wang Committed by Matthias Brugger
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dt-bindings: clock: mediatek: add missing required #reset-cells 



All ethsys, pciesys and ssusbsys internally include reset controller, so
explicitly add back these missing cell definitions to related bindings
and examples.

Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk@vger.kernel.org
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: default avatarStephen Boyd <sboyd@kernel.org>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 2c002a30

Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ Required Properties: 
	- "mediatek,mt2701-ethsys", "syscon"

	- "mediatek,mt7622-ethsys", "syscon"

- #clock-cells: Must be 1

- #reset-cells: Must be 1



The ethsys controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

Documentation/devicetree/bindings/arm/mediatek/mediatek,pciesys.txt

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ Required Properties: 
- compatible: Should be:

	- "mediatek,mt7622-pciesys", "syscon"

- #clock-cells: Must be 1

- #reset-cells: Must be 1



The PCIESYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ pciesys: pciesys@1a100800 { 
	compatible = "mediatek,mt7622-pciesys", "syscon";

	reg = <0 0x1a100800 0 0x1000>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};

Documentation/devicetree/bindings/arm/mediatek/mediatek,ssusbsys.txt

+2 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ Required Properties: 
- compatible: Should be:

	- "mediatek,mt7622-ssusbsys", "syscon"

- #clock-cells: Must be 1

- #reset-cells: Must be 1



The SSUSBSYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt
@@ -19,4 +20,5 @@ ssusbsys: ssusbsys@1a000000 { 
	compatible = "mediatek,mt7622-ssusbsys", "syscon";

	reg = <0 0x1a000000 0 0x1000>;

	#clock-cells = <1>;

	#reset-cells = <1>;

};