Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2c839337 authored by Iyappan Subramanian's avatar Iyappan Subramanian Committed by David S. Miller
Browse files

drivers: net: xgene: Add helper function 



This is a prepartion patch and adds xgene_enet_get_fpsel() helper
function to get buffer pool number.

Signed-off-by: default avatarIyappan Subramanian <isubramanian@apm.com>
Signed-off-by: default avatarQuan Nguyen <qnguyen@apm.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 397c5ad1

drivers/net/ethernet/apm/xgene/xgene_enet_cle.c

+2 −2
Original line number Diff line number Diff line
@@ -346,7 +346,7 @@ static int xgene_cle_set_rss_idt(struct xgene_enet_pdata *pdata) 
	for (i = 0; i < XGENE_CLE_IDT_ENTRIES; i++) {

		idx = i % pdata->rxq_cnt;

		pool_id = pdata->rx_ring[idx]->buf_pool->id;

		fpsel = xgene_enet_ring_bufnum(pool_id) - 0x20;

		fpsel = xgene_enet_get_fpsel(pool_id);

		dstqid = xgene_enet_dst_ring_num(pdata->rx_ring[idx]);

		nfpsel = 0;

		idt_reg = 0;
@@ -706,7 +706,7 @@ static int xgene_enet_cle_init(struct xgene_enet_pdata *pdata) 


	def_qid = xgene_enet_dst_ring_num(pdata->rx_ring[0]);

	pool_id = pdata->rx_ring[0]->buf_pool->id;

	def_fpsel = xgene_enet_ring_bufnum(pool_id) - 0x20;

	def_fpsel = xgene_enet_get_fpsel(pool_id);



	memset(dbptr, 0, sizeof(struct xgene_cle_dbptr) * DB_MAX_PTRS);

	dbptr[DB_RES_ACCEPT].fpsel =  def_fpsel;

drivers/net/ethernet/apm/xgene/xgene_enet_hw.c

+7 −12
Original line number Diff line number Diff line
@@ -555,7 +555,7 @@ static void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata, 
	u32 cb;

	u32 fpsel;



	fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;

	fpsel = xgene_enet_get_fpsel(bufpool_id);



	xgene_enet_rd_csr(pdata, CLE_BYPASS_REG0_0_ADDR, &cb);

	cb |= CFG_CLE_BYPASS_EN0;
@@ -652,16 +652,14 @@ static int xgene_enet_reset(struct xgene_enet_pdata *pdata) 
static void xgene_enet_clear(struct xgene_enet_pdata *pdata,

			     struct xgene_enet_desc_ring *ring)

{

	u32 addr, val, data;



	val = xgene_enet_ring_bufnum(ring->id);

	u32 addr, data;



	if (xgene_enet_is_bufpool(ring->id)) {

		addr = ENET_CFGSSQMIFPRESET_ADDR;

		data = BIT(val - 0x20);

		data = BIT(xgene_enet_get_fpsel(ring->id));

	} else {

		addr = ENET_CFGSSQMIWQRESET_ADDR;

		data = BIT(val);

		data = BIT(xgene_enet_ring_bufnum(ring->id));

	}



	xgene_enet_wr_ring_if(pdata, addr, data);
@@ -671,24 +669,21 @@ static void xgene_gport_shutdown(struct xgene_enet_pdata *pdata) 
{

	struct device *dev = &pdata->pdev->dev;

	struct xgene_enet_desc_ring *ring;

	u32 pb, val;

	u32 pb;

	int i;



	pb = 0;

	for (i = 0; i < pdata->rxq_cnt; i++) {

		ring = pdata->rx_ring[i]->buf_pool;

		pb |= BIT(xgene_enet_get_fpsel(ring->id));



		val = xgene_enet_ring_bufnum(ring->id);

		pb |= BIT(val - 0x20);

	}

	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb);



	pb = 0;

	for (i = 0; i < pdata->txq_cnt; i++) {

		ring = pdata->tx_ring[i];



		val = xgene_enet_ring_bufnum(ring->id);

		pb |= BIT(val);

		pb |= BIT(xgene_enet_ring_bufnum(ring->id));

	}

	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQRESET_ADDR, pb);

drivers/net/ethernet/apm/xgene/xgene_enet_hw.h

+8 −0
Original line number Diff line number Diff line
@@ -346,6 +346,14 @@ static inline bool xgene_enet_is_bufpool(u16 id) 
	return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;

}



static inline u8 xgene_enet_get_fpsel(u16 id)

{

	if (xgene_enet_is_bufpool(id))

		return xgene_enet_ring_bufnum(id) - RING_BUFNUM_BUFPOOL;



	return 0;

}



static inline u16 xgene_enet_get_numslots(u16 id, u32 size)

{

	bool is_bufpool = xgene_enet_is_bufpool(id);

drivers/net/ethernet/apm/xgene/xgene_enet_sgmac.c

+7 −13
Original line number Diff line number Diff line
@@ -501,7 +501,7 @@ static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p, 
	data = CFG_CLE_BYPASS_EN0;

	xgene_enet_wr_csr(p, cle_bypass_reg0 + offset, data);



	fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;

	fpsel = xgene_enet_get_fpsel(bufpool_id);

	data = CFG_CLE_DSTQID0(dst_ring_num) | CFG_CLE_FPSEL0(fpsel);

	xgene_enet_wr_csr(p, cle_bypass_reg1 + offset, data);

}
@@ -509,16 +509,14 @@ static void xgene_enet_cle_bypass(struct xgene_enet_pdata *p, 
static void xgene_enet_clear(struct xgene_enet_pdata *pdata,

			     struct xgene_enet_desc_ring *ring)

{

	u32 addr, val, data;



	val = xgene_enet_ring_bufnum(ring->id);

	u32 addr, data;



	if (xgene_enet_is_bufpool(ring->id)) {

		addr = ENET_CFGSSQMIFPRESET_ADDR;

		data = BIT(val - 0x20);

		data = BIT(xgene_enet_get_fpsel(ring->id));

	} else {

		addr = ENET_CFGSSQMIWQRESET_ADDR;

		data = BIT(val);

		data = BIT(xgene_enet_ring_bufnum(ring->id));

	}



	xgene_enet_wr_ring_if(pdata, addr, data);
@@ -528,24 +526,20 @@ static void xgene_enet_shutdown(struct xgene_enet_pdata *p) 
{

	struct device *dev = &p->pdev->dev;

	struct xgene_enet_desc_ring *ring;

	u32 pb, val;

	u32 pb;

	int i;



	pb = 0;

	for (i = 0; i < p->rxq_cnt; i++) {

		ring = p->rx_ring[i]->buf_pool;



		val = xgene_enet_ring_bufnum(ring->id);

		pb |= BIT(val - 0x20);

		pb |= BIT(xgene_enet_get_fpsel(ring->id));

	}

	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIFPRESET_ADDR, pb);



	pb = 0;

	for (i = 0; i < p->txq_cnt; i++) {

		ring = p->tx_ring[i];



		val = xgene_enet_ring_bufnum(ring->id);

		pb |= BIT(val);

		pb |= BIT(xgene_enet_ring_bufnum(ring->id));

	}

	xgene_enet_wr_ring_if(p, ENET_CFGSSQMIWQRESET_ADDR, pb);

drivers/net/ethernet/apm/xgene/xgene_enet_xgmac.c

+7 −13
Original line number Diff line number Diff line
@@ -359,7 +359,7 @@ static void xgene_enet_xgcle_bypass(struct xgene_enet_pdata *pdata, 
	CFG_CLE_IP_PROTOCOL0_SET(&cb, 3);

	xgene_enet_wr_csr(pdata, XCLE_BYPASS_REG0_ADDR, cb);



	fpsel = xgene_enet_ring_bufnum(bufpool_id) - 0x20;

	fpsel = xgene_enet_get_fpsel(bufpool_id);

	xgene_enet_rd_csr(pdata, XCLE_BYPASS_REG1_ADDR, &cb);

	CFG_CLE_DSTQID0_SET(&cb, dst_ring_num);

	CFG_CLE_FPSEL0_SET(&cb, fpsel);
@@ -370,24 +370,20 @@ static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata) 
{

	struct device *dev = &pdata->pdev->dev;

	struct xgene_enet_desc_ring *ring;

	u32 pb, val;

	u32 pb;

	int i;



	pb = 0;

	for (i = 0; i < pdata->rxq_cnt; i++) {

		ring = pdata->rx_ring[i]->buf_pool;



		val = xgene_enet_ring_bufnum(ring->id);

		pb |= BIT(val - 0x20);

		pb |= BIT(xgene_enet_get_fpsel(ring->id));

	}

	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIFPRESET_ADDR, pb);



	pb = 0;

	for (i = 0; i < pdata->txq_cnt; i++) {

		ring = pdata->tx_ring[i];



		val = xgene_enet_ring_bufnum(ring->id);

		pb |= BIT(val);

		pb |= BIT(xgene_enet_ring_bufnum(ring->id));

	}

	xgene_enet_wr_ring_if(pdata, ENET_CFGSSQMIWQRESET_ADDR, pb);
@@ -400,16 +396,14 @@ static void xgene_enet_shutdown(struct xgene_enet_pdata *pdata) 
static void xgene_enet_clear(struct xgene_enet_pdata *pdata,

			     struct xgene_enet_desc_ring *ring)

{

	u32 addr, val, data;



	val = xgene_enet_ring_bufnum(ring->id);

	u32 addr, data;



	if (xgene_enet_is_bufpool(ring->id)) {

		addr = ENET_CFGSSQMIFPRESET_ADDR;

		data = BIT(val - 0x20);

		data = BIT(xgene_enet_get_fpsel(ring->id));

	} else {

		addr = ENET_CFGSSQMIWQRESET_ADDR;

		data = BIT(val);

		data = BIT(xgene_enet_ring_bufnum(ring->id));

	}



	xgene_enet_wr_ring_if(pdata, addr, data);