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Commit 2c3d68ab authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'msm-next' of git://people.freedesktop.org/~robclark/linux into drm-next 

Mostly cleanups, fixes, and 'struct fence' conversion this time
around, with one reservation patch which is a-b Sumit (which the fence
conversion patches depend on).

* 'msm-next' of git://people.freedesktop.org/~robclark/linux: (25 commits)
  drm/msm: Drop load/unload drm_driver ops
  drm/msm: Centralize connector registration/unregistration
  drm/msm/hdmi: Prevent gpio_free related kernel warnings
  drm/msm: print offender task name on hangcheck recovery
  drm/msm: fix leak in failed submit path
  drm/msm: de-indent submit_create()
  drm/msm: drop return from gpu->submit()
  drm/msm/mdp4: Don't manage DSI PLL regulators in MDP driver
  drm/msm/edp: Drop regulator_set_voltage call
  drm/msm/dsi: Fix regulator API abuse
  drm/msm: Move call to PTR_ERR_OR_ZERO after reassignment
  drm/msm/mdp: Add support for more RGBX formats
  drm: msm: remove unused variable
  drm/msm: fix ->last_fence() after recover
  drm/msm: 'struct fence' conversion
  drm/msm: remove fence_cbs
  drm/msm: introduce msm_fence_context
  drm/msm: split locking and pinning BO's
  drm/msm/gpu: simplify tracking in-flight bo's
  drm/msm: split out timeout_to_jiffies helper
  ...
parents 2958cf0e 2b669875

drivers/gpu/drm/msm/Kconfig

+7 −0
Original line number Diff line number Diff line
@@ -23,6 +23,13 @@ config DRM_MSM_REGISTER_LOGGING 
	  that can be parsed by envytools demsm tool.  If enabled, register

	  logging can be switched on via msm.reglog=y module param.



config DRM_MSM_HDMI_HDCP

	bool "Enable HDMI HDCP support in MSM DRM driver"

	depends on DRM_MSM && QCOM_SCM

	default y

	help

	  Choose this option to enable HDCP state machine



config DRM_MSM_DSI

	bool "Enable DSI support in MSM DRM driver"

	depends on DRM_MSM

drivers/gpu/drm/msm/Makefile

+4 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ msm-y := \ 
	hdmi/hdmi_audio.o \

	hdmi/hdmi_bridge.o \

	hdmi/hdmi_connector.o \

	hdmi/hdmi_hdcp.o \

	hdmi/hdmi_i2c.o \

	hdmi/hdmi_phy.o \

	hdmi/hdmi_phy_8960.o \
@@ -40,8 +39,10 @@ msm-y := \ 
	mdp/mdp5/mdp5_plane.o \

	mdp/mdp5/mdp5_smp.o \

	msm_atomic.o \

	msm_debugfs.o \

	msm_drv.o \

	msm_fb.o \

	msm_fence.o \

	msm_gem.o \

	msm_gem_prime.o \

	msm_gem_submit.o \
@@ -56,6 +57,8 @@ msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o 
msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_pll_8960.o

msm-$(CONFIG_COMMON_CLK) += hdmi/hdmi_phy_8996.o



msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o



msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \

			mdp/mdp4/mdp4_dsi_encoder.o \

			dsi/dsi_cfg.o \

drivers/gpu/drm/msm/adreno/adreno_gpu.c

+7 −9
Original line number Diff line number Diff line
@@ -120,8 +120,8 @@ void adreno_recover(struct msm_gpu *gpu) 
	/* reset ringbuffer: */

	gpu->rb->cur = gpu->rb->start;



	/* reset completed fence seqno, just discard anything pending: */

	adreno_gpu->memptrs->fence = gpu->submitted_fence;

	/* reset completed fence seqno: */

	adreno_gpu->memptrs->fence = gpu->fctx->completed_fence;

	adreno_gpu->memptrs->rptr  = 0;

	adreno_gpu->memptrs->wptr  = 0;
@@ -133,7 +133,7 @@ void adreno_recover(struct msm_gpu *gpu) 
	}

}



int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

		struct msm_file_private *ctx)

{

	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
@@ -168,7 +168,7 @@ int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 
		OUT_PKT2(ring);



	OUT_PKT0(ring, REG_AXXX_CP_SCRATCH_REG2, 1);

	OUT_RING(ring, submit->fence);

	OUT_RING(ring, submit->fence->seqno);



	if (adreno_is_a3xx(adreno_gpu) || adreno_is_a4xx(adreno_gpu)) {

		/* Flush HLSQ lazy updates to make sure there is nothing
@@ -185,7 +185,7 @@ int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 
	OUT_PKT3(ring, CP_EVENT_WRITE, 3);

	OUT_RING(ring, CACHE_FLUSH_TS);

	OUT_RING(ring, rbmemptr(adreno_gpu, fence));

	OUT_RING(ring, submit->fence);

	OUT_RING(ring, submit->fence->seqno);



	/* we could maybe be clever and only CP_COND_EXEC the interrupt: */

	OUT_PKT3(ring, CP_INTERRUPT, 1);
@@ -212,8 +212,6 @@ int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, 
#endif



	gpu->funcs->flush(gpu);



	return 0;

}



void adreno_flush(struct msm_gpu *gpu)
@@ -254,7 +252,7 @@ void adreno_show(struct msm_gpu *gpu, struct seq_file *m) 
			adreno_gpu->rev.patchid);



	seq_printf(m, "fence:    %d/%d\n", adreno_gpu->memptrs->fence,

			gpu->submitted_fence);

			gpu->fctx->last_fence);

	seq_printf(m, "rptr:     %d\n", get_rptr(adreno_gpu));

	seq_printf(m, "wptr:     %d\n", adreno_gpu->memptrs->wptr);

	seq_printf(m, "rb wptr:  %d\n", get_wptr(gpu->rb));
@@ -295,7 +293,7 @@ void adreno_dump_info(struct msm_gpu *gpu) 
			adreno_gpu->rev.patchid);



	printk("fence:    %d/%d\n", adreno_gpu->memptrs->fence,

			gpu->submitted_fence);

			gpu->fctx->last_fence);

	printk("rptr:     %d\n", get_rptr(adreno_gpu));

	printk("wptr:     %d\n", adreno_gpu->memptrs->wptr);

	printk("rb wptr:  %d\n", get_wptr(gpu->rb));

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+1 −1
Original line number Diff line number Diff line
@@ -238,7 +238,7 @@ int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value); 
int adreno_hw_init(struct msm_gpu *gpu);

uint32_t adreno_last_fence(struct msm_gpu *gpu);

void adreno_recover(struct msm_gpu *gpu);

int adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,

		struct msm_file_private *ctx);

void adreno_flush(struct msm_gpu *gpu);

void adreno_idle(struct msm_gpu *gpu);

drivers/gpu/drm/msm/dsi/dsi.h

+0 −2
Original line number Diff line number Diff line
@@ -41,8 +41,6 @@ enum msm_dsi_phy_type { 
/* Regulators for DSI devices */

struct dsi_reg_entry {

	char name[32];

	int min_voltage;

	int max_voltage;

	int enable_load;

	int disable_load;

};