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Commit 2bbb0c0e authored by Vicente Bergas's avatar Vicente Bergas Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: move rk3399-sapphire PCIe to excavator baseboard 



The PCIe signals are routed through the connector to the baseboard.

Signed-off-by: default avatarVicente Bergas <vicencb@gmail.com>
Reviewed-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent e702e13f

arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dts

+15 −0
Original line number Diff line number Diff line
@@ -190,6 +190,21 @@ 
	status = "okay";

};



&pcie_phy {

	status = "okay";

};



&pcie0 {

	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;

	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;

	assigned-clock-rates = <100000000>;

	ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;

	num-lanes = <4>;

	pinctrl-names = "default";

	pinctrl-0 = <&pcie_clkreqn_cpm>;

	status = "okay";

};



&pinctrl {

	sdio-pwrseq {

		wifi_enable_h: wifi-enable-h {

arch/arm64/boot/dts/rockchip/rk3399-sapphire.dtsi

+0 −15
Original line number Diff line number Diff line
@@ -471,21 +471,6 @@ 
	gpio1830-supply = <&vcc_3v0>;

};



&pcie_phy {

	status = "okay";

};



&pcie0 {

	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;

	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;

	assigned-clock-rates = <100000000>;

	ep-gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_HIGH>;

	num-lanes = <4>;

	pinctrl-names = "default";

	pinctrl-0 = <&pcie_clkreqn_cpm>;

	status = "okay";

};



&pmu_io_domains {

	pmu1830-supply = <&vcc_3v0>;

	status = "okay";