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Commit 2bb2a5d3 authored by Paul Walmsley's avatar Paul Walmsley
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ARM: OMAP2+: PRM: create PRM reset source API for the watchdog timer driver 



The OMAP watchdog timer driver needs to determine what caused the SoC
to reset for its GETBOOTSTATUS ioctl.  So, define a set of standard
reset sources across OMAP SoCs.  For OMAP2xxx, 3xxx, and 4xxx SoCs,
define mappings from the SoC-specific reset source register bits to
the standardized reset source IDs.  Create SoC-specific PRM functions
that read the appropriate per-SoC register and use the mapping to
return the standardized reset bits.  Register the SoC-specific PRM
functions with the common PRM code via prm_register().  Create a
function in the common PRM code, prm_read_reset_sources(), that
calls the SoC-specific function, registered during boot.

This patch does not yet handle some SoCs, such as AM33xx.  Those SoCs
were not handled by the code this will replace.

Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent b5c5353d

arch/arm/mach-omap2/prm-regbits-24xx.h

+4 −0
Original line number Diff line number Diff line
@@ -209,9 +209,13 @@ 


/* RM_RSTST_WKUP specific bits */

/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */

#define OMAP24XX_EXTWMPU_RST_SHIFT			6

#define OMAP24XX_EXTWMPU_RST_MASK			(1 << 6)

#define OMAP24XX_SECU_WD_RST_SHIFT			5

#define OMAP24XX_SECU_WD_RST_MASK			(1 << 5)

#define OMAP24XX_MPU_WD_RST_SHIFT			4

#define OMAP24XX_MPU_WD_RST_MASK			(1 << 4)

#define OMAP24XX_SECU_VIOL_RST_SHIFT			3

#define OMAP24XX_SECU_VIOL_RST_MASK			(1 << 3)



/* PM_WKEN_WKUP specific bits */

arch/arm/mach-omap2/prm-regbits-34xx.h

+10 −0
Original line number Diff line number Diff line
@@ -509,15 +509,25 @@ 
#define OMAP3430_RSTTIME1_MASK				(0xff << 0)



/* PRM_RSTST */

#define OMAP3430_ICECRUSHER_RST_SHIFT			10

#define OMAP3430_ICECRUSHER_RST_MASK			(1 << 10)

#define OMAP3430_ICEPICK_RST_SHIFT			9

#define OMAP3430_ICEPICK_RST_MASK			(1 << 9)

#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_SHIFT		8

#define OMAP3430_VDD2_VOLTAGE_MANAGER_RST_MASK		(1 << 8)

#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_SHIFT		7

#define OMAP3430_VDD1_VOLTAGE_MANAGER_RST_MASK		(1 << 7)

#define OMAP3430_EXTERNAL_WARM_RST_SHIFT		6

#define OMAP3430_EXTERNAL_WARM_RST_MASK			(1 << 6)

#define OMAP3430_SECURE_WD_RST_SHIFT			5

#define OMAP3430_SECURE_WD_RST_MASK			(1 << 5)

#define OMAP3430_MPU_WD_RST_SHIFT			4

#define OMAP3430_MPU_WD_RST_MASK			(1 << 4)

#define OMAP3430_SECURITY_VIOL_RST_SHIFT		3

#define OMAP3430_SECURITY_VIOL_RST_MASK			(1 << 3)

#define OMAP3430_GLOBAL_SW_RST_SHIFT			1

#define OMAP3430_GLOBAL_SW_RST_MASK			(1 << 1)

#define OMAP3430_GLOBAL_COLD_RST_SHIFT			0

#define OMAP3430_GLOBAL_COLD_RST_MASK			(1 << 0)



/* PRM_VOLTCTRL */

arch/arm/mach-omap2/prm.h

+43 −1
Original line number Diff line number Diff line
@@ -52,16 +52,58 @@ 
#define OMAP_POWERSTATE_SHIFT				0

#define OMAP_POWERSTATE_MASK				(0x3 << 0)



/*

 * Standardized OMAP reset source bits

 *

 * To the extent these happen to match the hardware register bit

 * shifts, it's purely coincidental.  Used by omap-wdt.c.

 * OMAP_UNKNOWN_RST_SRC_ID_SHIFT is a special value, used whenever

 * there are any bits remaining in the global PRM_RSTST register that

 * haven't been identified, or when the PRM code for the current SoC

 * doesn't know how to interpret the register.

 */

#define OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT			0

#define OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT			1

#define OMAP_SECU_VIOL_RST_SRC_ID_SHIFT				2

#define OMAP_MPU_WD_RST_SRC_ID_SHIFT				3

#define OMAP_SECU_WD_RST_SRC_ID_SHIFT				4

#define OMAP_EXTWARM_RST_SRC_ID_SHIFT				5

#define OMAP_VDD_MPU_VM_RST_SRC_ID_SHIFT			6

#define OMAP_VDD_IVA_VM_RST_SRC_ID_SHIFT			7

#define OMAP_VDD_CORE_VM_RST_SRC_ID_SHIFT			8

#define OMAP_ICEPICK_RST_SRC_ID_SHIFT				9

#define OMAP_ICECRUSHER_RST_SRC_ID_SHIFT			10

#define OMAP_C2C_RST_SRC_ID_SHIFT				11

#define OMAP_UNKNOWN_RST_SRC_ID_SHIFT				12



#ifndef __ASSEMBLER__



/**

 * struct prm_reset_src_map - map register bitshifts to standard bitshifts

 * @reg_shift: bitshift in the PRM reset source register

 * @std_shift: bitshift equivalent in the standard reset source list

 *

 * The fields are signed because -1 is used as a terminator.

 */

struct prm_reset_src_map {

	s8 reg_shift;

	s8 std_shift;

};



/**

 * struct prm_ll_data - fn ptrs to per-SoC PRM function implementations

 * @read_reset_sources: ptr to the Soc PRM-specific get_reset_source impl

 */

struct prm_ll_data {};

struct prm_ll_data {

	u32 (*read_reset_sources)(void);

};



extern int prm_register(struct prm_ll_data *pld);

extern int prm_unregister(struct prm_ll_data *pld);



extern u32 prm_read_reset_sources(void);



#endif





#endif

arch/arm/mach-omap2/prm2xxx.c

+68 −0
Original line number Diff line number Diff line
@@ -29,6 +29,46 @@ 
#include "cm2xxx_3xxx.h"

#include "prm-regbits-24xx.h"



/*

 * omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP

 *   hardware register (which are specific to the OMAP2xxx SoCs) to

 *   reset source ID bit shifts (which is an OMAP SoC-independent

 *   enumeration)

 */

static struct prm_reset_src_map omap2xxx_prm_reset_src_map[] = {

	{ OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },

	{ OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },

	{ OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },

	{ OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },

	{ OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },

	{ OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },

	{ -1, -1 },

};



/**

 * omap2xxx_prm_read_reset_sources - return the last SoC reset source

 *

 * Return a u32 representing the last reset sources of the SoC.  The

 * returned reset source bits are standardized across OMAP SoCs.

 */

static u32 omap2xxx_prm_read_reset_sources(void)

{

	struct prm_reset_src_map *p;

	u32 r = 0;

	u32 v;



	v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);



	p = omap2xxx_prm_reset_src_map;

	while (p->reg_shift >= 0 && p->std_shift >= 0) {

		if (v & (1 << p->reg_shift))

			r |= 1 << p->std_shift;

		p++;

	}



	return r;

}



int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)

{

	omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
@@ -56,3 +96,31 @@ struct pwrdm_ops omap2_pwrdm_operations = { 
	.pwrdm_read_mem_retst	= omap2_pwrdm_read_mem_retst,

	.pwrdm_wait_transition	= omap2_pwrdm_wait_transition,

};



/*

 *

 */



static struct prm_ll_data omap2xxx_prm_ll_data = {

	.read_reset_sources = &omap2xxx_prm_read_reset_sources,

};



static int __init omap2xxx_prm_init(void)

{

	if (!cpu_is_omap24xx())

		return 0;



	return prm_register(&omap2xxx_prm_ll_data);

}

subsys_initcall(omap2xxx_prm_init);



static void __exit omap2xxx_prm_exit(void)

{

	if (!cpu_is_omap24xx())

		return;



	/* Should never happen */

	WARN(prm_unregister(&omap2xxx_prm_ll_data),

	     "%s: prm_ll_data function pointer mismatch\n", __func__);

}

__exitcall(omap2xxx_prm_exit);

arch/arm/mach-omap2/prm2xxx.h

+4 −0
Original line number Diff line number Diff line
@@ -123,6 +123,10 @@ 
/* Function prototypes */

extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm);

extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm);



extern int __init prm2xxx_init(void);

extern int __exit prm2xxx_exit(void);



#endif



#endif