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Commit 2b555a4b authored by Paul Cercueil's avatar Paul Cercueil Committed by Stephen Boyd
Browse files

clk: ingenic: Add missing flag for UDC clock 



The UDC clock of the JZ4740 SoC can be gated, but the data structure
representing it was missing the CGU_CLK_GATE flag to make it work.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 574f4e80

drivers/clk/ingenic/jz4740-cgu.c

+1 −1
Original line number Original line Diff line number Diff line
@@ -161,7 +161,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = { 
	},

	},





	[JZ4740_CLK_UDC] = {

	[JZ4740_CLK_UDC] = {

		"udc", CGU_CLK_MUX | CGU_CLK_DIV,

		"udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,

		.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },

		.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },

		.mux = { CGU_REG_CPCCR, 29, 1 },

		.mux = { CGU_REG_CPCCR, 29, 1 },

		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },

		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },