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Commit 2b2fc72a authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-testing-2017-04-03' of... 

Merge tag 'drm-intel-testing-2017-04-03' of git://anongit.freedesktop.org/git/drm-intel into drm-next

Last 4.12 feature pile:

GVT updates:
- Add mdev attribute group for per-vgpu info
- Time slice based vGPU scheduling QoS support (Gao Ping)
- Initial KBL support for E3 server (Han Xu)
- other misc.

i915:
- lots and lots of small fixes and improvements all over
- refactor fw_domain code (Chris Wilson)
- improve guc code (Oscar Mateo)
- refactor cursor/sprite code, precompute more for less overhead in
  the critical path (Ville)
- refactor guc/huc fw loading code a bit (Michal Wajdeczko)

* tag 'drm-intel-testing-2017-04-03' of git://anongit.freedesktop.org/git/drm-intel: (121 commits)
  drm/i915: Update DRIVER_DATE to 20170403
  drm/i915: Clear gt.active_requests before checking idle status
  drm/i915/uc: Drop use of MISSING_CASE on trivial enums
  drm/i915: make a few DDI functions static
  drm/i915: Combine reset_all_global_seqno() loops into one
  drm/i915: Remove redudant wait for each engine to idle from seqno wrap
  drm/i915: Wait for all engines to be idle as part of i915_gem_wait_for_idle()
  drm/i915: Move retire-requests into i915_gem_wait_for_idle()
  drm/i915/uc: Move fw path check to fetch_uc_fw()
  drm/i915/huc: Remove unused intel_huc_fini()
  drm/i915/uc: Add intel_uc_fw_fini()
  drm/i915/uc: Add intel_uc_fw_type_repr()
  drm/i915/uc: Move intel_uc_fw_status_repr() to intel_uc.h
  drivers: gpu: drm: i915L intel_lpe_audio: Fix kerneldoc comments
  drm/i915: Suppress busy status for engines if wedged
  drm/i915: Do request retirement before marking engines as wedged
  drm/i915: Drop verbose and archaic "ring" from our internal engine names
  drm/i915: Use a dummy timeline name for a signaled fence
  drm/i915: Ironlake do_idle_maps w/a may be called w/o struct_mutex
  drm/i915/guc: Take enable_guc_loading check out of GEM core code
  ...
parents cdf5316b ba515d34

drivers/gpu/drm/i915/gvt/cmd_parser.c

+28 −14
Original line number Diff line number Diff line
@@ -1215,7 +1215,7 @@ static int gen8_check_mi_display_flip(struct parser_exec_state *s, 
	if (!info->async_flip)

		return 0;



	if (IS_SKYLAKE(dev_priv)) {

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		stride = vgpu_vreg(s->vgpu, info->stride_reg) & GENMASK(9, 0);

		tile = (vgpu_vreg(s->vgpu, info->ctrl_reg) &

				GENMASK(12, 10)) >> 10;
@@ -1243,7 +1243,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip( 


	set_mask_bits(&vgpu_vreg(vgpu, info->surf_reg), GENMASK(31, 12),

		      info->surf_val << 12);

	if (IS_SKYLAKE(dev_priv)) {

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		set_mask_bits(&vgpu_vreg(vgpu, info->stride_reg), GENMASK(9, 0),

			      info->stride_val);

		set_mask_bits(&vgpu_vreg(vgpu, info->ctrl_reg), GENMASK(12, 10),
@@ -1267,7 +1267,7 @@ static int decode_mi_display_flip(struct parser_exec_state *s, 


	if (IS_BROADWELL(dev_priv))

		return gen8_decode_mi_display_flip(s, info);

	if (IS_SKYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

		return skl_decode_mi_display_flip(s, info);



	return -ENODEV;
@@ -1278,7 +1278,9 @@ static int check_mi_display_flip(struct parser_exec_state *s, 
{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))

	if (IS_BROADWELL(dev_priv)

		|| IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv))

		return gen8_check_mi_display_flip(s, info);

	return -ENODEV;

}
@@ -1289,7 +1291,9 @@ static int update_plane_mmio_from_mi_display_flip( 
{

	struct drm_i915_private *dev_priv = s->vgpu->gvt->dev_priv;



	if (IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv))

	if (IS_BROADWELL(dev_priv)

		|| IS_SKYLAKE(dev_priv)

		|| IS_KABYLAKE(dev_priv))

		return gen8_update_plane_mmio_from_mi_display_flip(s, info);

	return -ENODEV;

}
@@ -1569,7 +1573,8 @@ static int batch_buffer_needs_scan(struct parser_exec_state *s) 
{

	struct intel_gvt *gvt = s->vgpu->gvt;



	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {

	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)

		|| IS_KABYLAKE(gvt->dev_priv)) {

		/* BDW decides privilege based on address space */

		if (cmd_val(s, 0) & (1 << 8))

			return 0;
@@ -2604,6 +2609,9 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 
	unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;

	struct parser_exec_state s;

	int ret = 0;

	struct intel_vgpu_workload *workload = container_of(wa_ctx,

				struct intel_vgpu_workload,

				wa_ctx);



	/* ring base is page aligned */

	if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, GTT_PAGE_SIZE)))
@@ -2618,14 +2626,14 @@ static int scan_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 


	s.buf_type = RING_BUFFER_INSTRUCTION;

	s.buf_addr_type = GTT_BUFFER;

	s.vgpu = wa_ctx->workload->vgpu;

	s.ring_id = wa_ctx->workload->ring_id;

	s.vgpu = workload->vgpu;

	s.ring_id = workload->ring_id;

	s.ring_start = wa_ctx->indirect_ctx.guest_gma;

	s.ring_size = ring_size;

	s.ring_head = gma_head;

	s.ring_tail = gma_tail;

	s.rb_va = wa_ctx->indirect_ctx.shadow_va;

	s.workload = wa_ctx->workload;

	s.workload = workload;



	ret = ip_gma_set(&s, gma_head);

	if (ret)
@@ -2708,12 +2716,15 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) 
{

	int ctx_size = wa_ctx->indirect_ctx.size;

	unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;

	struct intel_vgpu *vgpu = wa_ctx->workload->vgpu;

	struct intel_vgpu_workload *workload = container_of(wa_ctx,

					struct intel_vgpu_workload,

					wa_ctx);

	struct intel_vgpu *vgpu = workload->vgpu;

	struct drm_i915_gem_object *obj;

	int ret = 0;

	void *map;



	obj = i915_gem_object_create(wa_ctx->workload->vgpu->gvt->dev_priv,

	obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,

				     roundup(ctx_size + CACHELINE_BYTES,

					     PAGE_SIZE));

	if (IS_ERR(obj))
@@ -2733,8 +2744,8 @@ static int shadow_indirect_ctx(struct intel_shadow_wa_ctx *wa_ctx) 
		goto unmap_src;

	}



	ret = copy_gma_to_hva(wa_ctx->workload->vgpu,

				wa_ctx->workload->vgpu->gtt.ggtt_mm,

	ret = copy_gma_to_hva(workload->vgpu,

				workload->vgpu->gtt.ggtt_mm,

				guest_gma, guest_gma + ctx_size,

				map);

	if (ret < 0) {
@@ -2772,7 +2783,10 @@ static int combine_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx) 
int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)

{

	int ret;

	struct intel_vgpu *vgpu = wa_ctx->workload->vgpu;

	struct intel_vgpu_workload *workload = container_of(wa_ctx,

					struct intel_vgpu_workload,

					wa_ctx);

	struct intel_vgpu *vgpu = workload->vgpu;



	if (wa_ctx->indirect_ctx.size == 0)

		return 0;

drivers/gpu/drm/i915/gvt/display.c

+17 −5
Original line number Diff line number Diff line
@@ -161,8 +161,9 @@ static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = { 


#define DPCD_HEADER_SIZE        0xb



/* let the virtual display supports DP1.2 */

static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {

	0x11, 0x0a, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

	0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

};



static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
@@ -172,9 +173,20 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
			SDE_PORTC_HOTPLUG_CPT |

			SDE_PORTD_HOTPLUG_CPT);



	if (IS_SKYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {

		vgpu_vreg(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |

				SDE_PORTE_HOTPLUG_SPT);

		vgpu_vreg(vgpu, SKL_FUSE_STATUS) |=

				SKL_FUSE_DOWNLOAD_STATUS |

				SKL_FUSE_PG0_DIST_STATUS |

				SKL_FUSE_PG1_DIST_STATUS |

				SKL_FUSE_PG2_DIST_STATUS;

		vgpu_vreg(vgpu, LCPLL1_CTL) |=

				LCPLL_PLL_ENABLE |

				LCPLL_PLL_LOCK;

		vgpu_vreg(vgpu, LCPLL2_CTL) |= LCPLL_PLL_ENABLE;



	}



	if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {

		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
@@ -191,7 +203,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) 
		vgpu_vreg(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;

	}



	if (IS_SKYLAKE(dev_priv) &&

	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&

			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {

		vgpu_vreg(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;

	}
@@ -353,7 +365,7 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 
{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;



	if (IS_SKYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

		clean_virtual_dp_monitor(vgpu, PORT_D);

	else

		clean_virtual_dp_monitor(vgpu, PORT_B);
@@ -375,7 +387,7 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution) 


	intel_vgpu_init_i2c_edid(vgpu);



	if (IS_SKYLAKE(dev_priv))

	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))

		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,

						resolution);

	else

drivers/gpu/drm/i915/gvt/execlist.c

+5 −4
Original line number Diff line number Diff line
@@ -394,9 +394,11 @@ static void prepare_shadow_batch_buffer(struct intel_vgpu_workload *workload) 


static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)

{

	int ring_id = wa_ctx->workload->ring_id;

	struct i915_gem_context *shadow_ctx =

		wa_ctx->workload->vgpu->shadow_ctx;

	struct intel_vgpu_workload *workload = container_of(wa_ctx,

					struct intel_vgpu_workload,

					wa_ctx);

	int ring_id = workload->ring_id;

	struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;

	struct drm_i915_gem_object *ctx_obj =

		shadow_ctx->engine[ring_id].state->obj;

	struct execlist_ring_context *shadow_ring_context;
@@ -680,7 +682,6 @@ static int submit_context(struct intel_vgpu *vgpu, int ring_id, 
			CACHELINE_BYTES;

		workload->wa_ctx.per_ctx.guest_gma =

			per_ctx & PER_CTX_ADDR_MASK;

		workload->wa_ctx.workload = workload;



		WARN_ON(workload->wa_ctx.indirect_ctx.size && !(per_ctx & 0x1));

	}

drivers/gpu/drm/i915/gvt/gtt.c

+2 −1
Original line number Diff line number Diff line
@@ -2220,7 +2220,8 @@ int intel_gvt_init_gtt(struct intel_gvt *gvt) 


	gvt_dbg_core("init gtt\n");



	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {

	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)

		|| IS_KABYLAKE(gvt->dev_priv)) {

		gvt->gtt.pte_ops = &gen8_gtt_pte_ops;

		gvt->gtt.gma_ops = &gen8_gtt_gma_ops;

		gvt->gtt.mm_alloc_page_table = gen8_mm_alloc_page_table;

drivers/gpu/drm/i915/gvt/gvt.c

+18 −1
Original line number Diff line number Diff line
@@ -106,7 +106,8 @@ static void init_device_info(struct intel_gvt *gvt) 
	struct intel_gvt_device_info *info = &gvt->device_info;

	struct pci_dev *pdev = gvt->dev_priv->drm.pdev;



	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) {

	if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)

		|| IS_KABYLAKE(gvt->dev_priv)) {

		info->max_support_vgpus = 8;

		info->cfg_space_size = 256;

		info->mmio_size = 2 * 1024 * 1024;
@@ -143,6 +144,11 @@ static int gvt_service_thread(void *data) 
			intel_gvt_emulate_vblank(gvt);

			mutex_unlock(&gvt->lock);

		}



		if (test_and_clear_bit(INTEL_GVT_REQUEST_SCHED,

					(void *)&gvt->service_request)) {

			intel_gvt_schedule(gvt);

		}

	}



	return 0;
@@ -196,6 +202,8 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv) 


	idr_destroy(&gvt->vgpu_idr);



	intel_gvt_destroy_idle_vgpu(gvt->idle_vgpu);



	kfree(dev_priv->gvt);

	dev_priv->gvt = NULL;

}
@@ -214,6 +222,7 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv) 
int intel_gvt_init_device(struct drm_i915_private *dev_priv)

{

	struct intel_gvt *gvt;

	struct intel_vgpu *vgpu;

	int ret;



	/*
@@ -286,6 +295,14 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv) 
		goto out_clean_types;

	}



	vgpu = intel_gvt_create_idle_vgpu(gvt);

	if (IS_ERR(vgpu)) {

		ret = PTR_ERR(vgpu);

		gvt_err("failed to create idle vgpu\n");

		goto out_clean_types;

	}

	gvt->idle_vgpu = vgpu;



	gvt_dbg_core("gvt device initialization is done\n");

	dev_priv->gvt = gvt;

	return 0;