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Commit 2b254693 authored by Sascha Hauer's avatar Sascha Hauer
Browse files

ARM i.MX6: remove gate_mask from pllv3 



Now that the additional enable bits in the enet PLL are handled
as gates, the gate_mask is identical for all plls. Remove the
gate_mask from the code and use the BM_PLL_ENABLE bit for
enabling/disabling the PLL.

Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
Acked-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 7a04092c

arch/arm/mach-imx/clk-imx6q.c

+9 −9
Original line number Diff line number Diff line
@@ -198,15 +198,15 @@ int __init mx6q_clocks_init(void) 
	base = of_iomap(np, 0);

	WARN_ON(!base);



	/*                   type                               name         parent_name  base     gate_mask div_mask */

	clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,	"pll1_sys",	"osc", base,        0x2000,   0x7f);

	clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,	"pll2_bus",	"osc", base + 0x30, 0x2000,   0x1);

	clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,	"pll3_usb_otg",	"osc", base + 0x10, 0x2000,   0x3);

	clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,	"pll4_audio",	"osc", base + 0x70, 0x2000,   0x7f);

	clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,	"pll5_video",	"osc", base + 0xa0, 0x2000,   0x7f);

	clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,	"pll6_enet",	"osc", base + 0xe0, 0x2000,   0x3);

	clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,	"pll7_usb_host","osc", base + 0x20, 0x2000,   0x3);

	clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,	"pll8_mlb",	"osc", base + 0xd0, 0x2000,   0x0);

	/*                   type                               name         parent_name  base     div_mask */

	clk[pll1_sys]      = imx_clk_pllv3(IMX_PLLV3_SYS,	"pll1_sys",	"osc", base,        0x7f);

	clk[pll2_bus]      = imx_clk_pllv3(IMX_PLLV3_GENERIC,	"pll2_bus",	"osc", base + 0x30, 0x1);

	clk[pll3_usb_otg]  = imx_clk_pllv3(IMX_PLLV3_USB,	"pll3_usb_otg",	"osc", base + 0x10, 0x3);

	clk[pll4_audio]    = imx_clk_pllv3(IMX_PLLV3_AV,	"pll4_audio",	"osc", base + 0x70, 0x7f);

	clk[pll5_video]    = imx_clk_pllv3(IMX_PLLV3_AV,	"pll5_video",	"osc", base + 0xa0, 0x7f);

	clk[pll6_enet]     = imx_clk_pllv3(IMX_PLLV3_ENET,	"pll6_enet",	"osc", base + 0xe0, 0x3);

	clk[pll7_usb_host] = imx_clk_pllv3(IMX_PLLV3_USB,	"pll7_usb_host","osc", base + 0x20, 0x3);

	clk[pll8_mlb]      = imx_clk_pllv3(IMX_PLLV3_MLB,	"pll8_mlb",	"osc", base + 0xd0, 0x0);



	clk[usbphy1] = imx_clk_gate("usbphy1", "pll3_usb_otg", base + 0x10, 6);

	clk[usbphy2] = imx_clk_gate("usbphy2", "pll7_usb_host", base + 0x20, 6);

arch/arm/mach-imx/clk-pllv3.c

+3 −6
Original line number Diff line number Diff line
@@ -31,7 +31,6 @@ 
 * @clk_hw:	 clock source

 * @base:	 base address of PLL registers

 * @powerup_set: set POWER bit to power up the PLL

 * @gate_mask:	 mask of gate bits

 * @div_mask:	 mask of divider bits

 *

 * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
@@ -41,7 +40,6 @@ struct clk_pllv3 { 
	struct clk_hw	hw;

	void __iomem	*base;

	bool		powerup_set;

	u32		gate_mask;

	u32		div_mask;

};
@@ -89,7 +87,7 @@ static int clk_pllv3_enable(struct clk_hw *hw) 
	u32 val;



	val = readl_relaxed(pll->base);

	val |= pll->gate_mask;

	val |= BM_PLL_ENABLE;

	writel_relaxed(val, pll->base);



	return 0;
@@ -101,7 +99,7 @@ static void clk_pllv3_disable(struct clk_hw *hw) 
	u32 val;



	val = readl_relaxed(pll->base);

	val &= ~pll->gate_mask;

	val &= ~BM_PLL_ENABLE;

	writel_relaxed(val, pll->base);

}
@@ -307,7 +305,7 @@ static const struct clk_ops clk_pllv3_mlb_ops = { 


struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,

			  const char *parent_name, void __iomem *base,

			  u32 gate_mask, u32 div_mask)

			  u32 div_mask)

{

	struct clk_pllv3 *pll;

	const struct clk_ops *ops;
@@ -339,7 +337,6 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, 
		ops = &clk_pllv3_ops;

	}

	pll->base = base;

	pll->gate_mask = gate_mask;

	pll->div_mask = div_mask;



	init.name = name;

arch/arm/mach-imx/clk.h

+1 −2
Original line number Diff line number Diff line
@@ -22,8 +22,7 @@ enum imx_pllv3_type { 
};



struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name,

		const char *parent_name, void __iomem *base, u32 gate_mask,

		u32 div_mask);

		const char *parent_name, void __iomem *base, u32 div_mask);



struct clk *clk_register_gate2(struct device *dev, const char *name,

		const char *parent_name, unsigned long flags,