Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2abf3c0d authored by Lucas De Marchi's avatar Lucas De Marchi Committed by Rodrigo Vivi
Browse files

drm/i915: add platform tag to WA 



v2: add more missing platform tags
v3: change tag to cnp rather than using gen9,gen10

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20171205190118.7088-2-lucas.demarchi@intel.com
parent e0403cb9

drivers/gpu/drm/i915/intel_hdmi.c

+1 −1
Original line number Diff line number Diff line
@@ -1380,7 +1380,7 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) 
		}

	}



	/* Display WA #1139 */

	/* Display WA #1139: glk */

	if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&

	    crtc_state->base.adjusted_mode.htotal > 5460)

		return false;

drivers/gpu/drm/i915/intel_pm.c

+1 −1
Original line number Diff line number Diff line
@@ -8417,7 +8417,7 @@ static void cnp_init_clock_gating(struct drm_i915_private *dev_priv) 
	if (!HAS_PCH_CNP(dev_priv))

		return;



	/* Display WA #1181 */

	/* Display WA #1181: cnp */

	I915_WRITE(SOUTH_DSPCLK_GATE_D, I915_READ(SOUTH_DSPCLK_GATE_D) |

		   CNP_PWM_CGE_GATING_DISABLE);

}