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Commit 2a5cfec9 authored by Rajendra Nayak's avatar Rajendra Nayak Committed by Michael Turquette
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dt-bindings: Add #defines for IPQ806x lpass clock control



Add defines to make more human readable numbers for the lpass
clock controller found on IPQ806x SoCs. Also remove the PLL4
define in gcc to avoid #define conflicts because that clock
doesn't exist in gcc, instead it lives in lcc.

Signed-off-by: default avatarRajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Split off into separate patch]
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Tested-by: default avatarKenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
parent b3ee3eff
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+0 −1
Original line number Diff line number Diff line
@@ -238,7 +238,6 @@
#define PLL0_VOTE				221
#define PLL3					222
#define PLL3_VOTE				223
#define PLL4					224
#define PLL4_VOTE				225
#define PLL8					226
#define PLL8_VOTE				227
+30 −0
Original line number Diff line number Diff line
/*
 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef _DT_BINDINGS_CLK_LCC_IPQ806X_H
#define _DT_BINDINGS_CLK_LCC_IPQ806X_H

#define PLL4				0
#define MI2S_OSR_SRC			1
#define MI2S_OSR_CLK			2
#define MI2S_DIV_CLK			3
#define MI2S_BIT_DIV_CLK		4
#define MI2S_BIT_CLK			5
#define PCM_SRC				6
#define PCM_CLK_OUT			7
#define PCM_CLK				8
#define SPDIF_SRC			9
#define SPDIF_CLK			10
#define AHBIX_CLK			11

#endif