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Commit 2a5cbc15 authored by Srinivas Kandagatla's avatar Srinivas Kandagatla Committed by Andy Gross
Browse files

ARM: dts: apq8064: add gsbi4 with i2c node. 



This patch adds gsbi4 and i2c node.

Signed-off-by: default avatarSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 7788d439

arch/arm/boot/dts/qcom-apq8064-pins.dtsi

+25 −0
Original line number Diff line number Diff line
@@ -90,6 +90,31 @@ 
		};

	};



	i2c4_pins: i2c4 {

		mux {

			pins = "gpio12", "gpio13";

			function = "gsbi4";

		};



		pinconf {

			pins = "gpio12", "gpio13";

			drive-strength = <16>;

			bias-disable;

		};

	};



	i2c4_pins_sleep: i2c4_pins_sleep {

		mux {

			pins = "gpio12", "gpio13";

			function = "gpio";

		};

		pinconf {

			pins = "gpio12", "gpio13";

			drive-strength = <2>;

			bias-disable = <0>;

		};

	};



	spi5_default: spi5_default {

		pinmux {

			pins = "gpio51", "gpio52", "gpio54";

arch/arm/boot/dts/qcom-apq8064.dtsi

+23 −0
Original line number Diff line number Diff line
@@ -289,6 +289,29 @@ 
			};

		};



		gsbi4: gsbi@16300000 {

			status = "disabled";

			compatible = "qcom,gsbi-v1.0.0";

			cell-index = <4>;

			reg = <0x16300000 0x03>;

			clocks = <&gcc GSBI4_H_CLK>;

			clock-names = "iface";

			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			gsbi4_i2c: i2c@16380000 {

				compatible = "qcom,i2c-qup-v1.1.1";

				pinctrl-0 = <&i2c4_pins &i2c4_pins_sleep>;

				pinctrl-names = "default", "sleep";

				reg = <0x16380000 0x1000>;

				interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;

				clocks = <&gcc GSBI4_QUP_CLK>,

					 <&gcc GSBI4_H_CLK>;

				clock-names = "core", "iface";

			};

		};



		gsbi5: gsbi@1a200000 {

			status = "disabled";

			compatible = "qcom,gsbi-v1.0.0";