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Commit 28c20cc7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2018-07-20' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Just two sets of driver fixes this week to follow up on the set from
  earlier in the week and hopefully get me realigned schedule wise.

  amdgpu:
   - ACP fix for boards with multiple I2S instances
   - DP fix for CZ, vega
   - hybrid laptop fixes
   - Resume regression fix

  nouveau:
   - large memory systems and Pascal fix
   - MST race fixes
   - runtime PM fix"

* tag 'drm-fixes-2018-07-20' of git://anongit.freedesktop.org/drm/drm:
  drm/nouveau/fb/gp100-: disable address remapper
  drm/amd/amdgpu: creating two I2S instances for stoney/cz (v2)
  drm/amdgpu: add another ATPX quirk for TOPAZ
  drm/amd/display: Fix DP HBR2 Eye Diagram Pattern on Carrizo
  drm/amdgpu: Make sure IB tests flushed after IP resume
  drm/nouveau: Set DRIVER_ATOMIC cap earlier to fix debugfs
  drm/nouveau: Remove bogus crtc check in pmops_runtime_idle
  drm/nouveau/drm/nouveau: Fix runtime PM leak in nv50_disp_atomic_commit()
  drm/nouveau: Avoid looping through fake MST connectors
  drm/nouveau: Use drm_connector_list_iter_* for iterating connectors
  drm/nouveau/gem: off by one bugs in nouveau_gem_pushbuf_reloc_apply()
  drm/nouveau/kms/nv50-: ensure window updates are submitted when flushing mst disables
parents fb7d1bcf 02e546ea

drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c

+37 −10
Original line number Diff line number Diff line
@@ -57,6 +57,10 @@ 
#define ACP_I2S_COMP2_CAP_REG_OFFSET		0xa8

#define ACP_I2S_COMP1_PLAY_REG_OFFSET		0x6c

#define ACP_I2S_COMP2_PLAY_REG_OFFSET		0x68

#define ACP_BT_PLAY_REGS_START			0x14970

#define ACP_BT_PLAY_REGS_END			0x14a24

#define ACP_BT_COMP1_REG_OFFSET			0xac

#define ACP_BT_COMP2_REG_OFFSET			0xa8



#define mmACP_PGFSM_RETAIN_REG			0x51c9

#define mmACP_PGFSM_CONFIG_REG			0x51ca
@@ -77,7 +81,7 @@ 
#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE	0x000000FF



#define ACP_TIMEOUT_LOOP			0x000000FF

#define ACP_DEVS				3

#define ACP_DEVS				4

#define ACP_SRC_ID				162



enum {
@@ -316,14 +320,13 @@ static int acp_hw_init(void *handle) 
	if (adev->acp.acp_cell == NULL)

		return -ENOMEM;



	adev->acp.acp_res = kcalloc(4, sizeof(struct resource), GFP_KERNEL);



	adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);

	if (adev->acp.acp_res == NULL) {

		kfree(adev->acp.acp_cell);

		return -ENOMEM;

	}



	i2s_pdata = kcalloc(2, sizeof(struct i2s_platform_data), GFP_KERNEL);

	i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);

	if (i2s_pdata == NULL) {

		kfree(adev->acp.acp_res);

		kfree(adev->acp.acp_cell);
@@ -358,6 +361,20 @@ static int acp_hw_init(void *handle) 
	i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;

	i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;



	i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;

	switch (adev->asic_type) {

	case CHIP_STONEY:

		i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;

		break;

	default:

		break;

	}



	i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;

	i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;

	i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;

	i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;



	adev->acp.acp_res[0].name = "acp2x_dma";

	adev->acp.acp_res[0].flags = IORESOURCE_MEM;

	adev->acp.acp_res[0].start = acp_base;
@@ -373,13 +390,18 @@ static int acp_hw_init(void *handle) 
	adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;

	adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;



	adev->acp.acp_res[3].name = "acp2x_dma_irq";

	adev->acp.acp_res[3].flags = IORESOURCE_IRQ;

	adev->acp.acp_res[3].start = amdgpu_irq_create_mapping(adev, 162);

	adev->acp.acp_res[3].end = adev->acp.acp_res[3].start;

	adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";

	adev->acp.acp_res[3].flags = IORESOURCE_MEM;

	adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;

	adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;



	adev->acp.acp_res[4].name = "acp2x_dma_irq";

	adev->acp.acp_res[4].flags = IORESOURCE_IRQ;

	adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);

	adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;



	adev->acp.acp_cell[0].name = "acp_audio_dma";

	adev->acp.acp_cell[0].num_resources = 4;

	adev->acp.acp_cell[0].num_resources = 5;

	adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];

	adev->acp.acp_cell[0].platform_data = &adev->asic_type;

	adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
@@ -396,6 +418,12 @@ static int acp_hw_init(void *handle) 
	adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];

	adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);



	adev->acp.acp_cell[3].name = "designware-i2s";

	adev->acp.acp_cell[3].num_resources = 1;

	adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];

	adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];

	adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);



	r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,

								ACP_DEVS);

	if (r)
@@ -451,7 +479,6 @@ static int acp_hw_init(void *handle) 
	val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);

	val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;

	cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);



	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c

+1 −0
Original line number Diff line number Diff line
@@ -575,6 +575,7 @@ static const struct amdgpu_px_quirk amdgpu_px_quirk_list[] = { 
	{ 0x1002, 0x6900, 0x1002, 0x0124, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1028, 0x0812, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1028, 0x0813, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0x1002, 0x6900, 0x1025, 0x125A, AMDGPU_PX_QUIRK_FORCE_ATPX },

	{ 0, 0, 0, 0, 0 },

};

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+3 −0
Original line number Diff line number Diff line
@@ -2747,6 +2747,9 @@ int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) 
	if (r)

		return r;



	/* Make sure IB tests flushed */

	flush_delayed_work(&adev->late_init_work);



	/* blat the mode back in */

	if (fbcon) {

		if (!amdgpu_device_has_dc_support(adev)) {

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+3 −5
Original line number Diff line number Diff line
@@ -1767,12 +1767,10 @@ static void dp_test_send_link_training(struct dc_link *link) 
	dp_retrain_link_dp_test(link, &link_settings, false);

}



/* TODO hbr2 compliance eye output is unstable

/* TODO Raven hbr2 compliance eye output is unstable

 * (toggling on and off) with debugger break

 * This caueses intermittent PHY automation failure

 * Need to look into the root cause */

static uint8_t force_tps4_for_cp2520 = 1;



static void dp_test_send_phy_test_pattern(struct dc_link *link)

{

	union phy_test_pattern dpcd_test_pattern;
@@ -1832,13 +1830,13 @@ static void dp_test_send_phy_test_pattern(struct dc_link *link) 
		break;

	case PHY_TEST_PATTERN_CP2520_1:

		/* CP2520 pattern is unstable, temporarily use TPS4 instead */

		test_pattern = (force_tps4_for_cp2520 == 1) ?

		test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?

				DP_TEST_PATTERN_TRAINING_PATTERN4 :

				DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;

		break;

	case PHY_TEST_PATTERN_CP2520_2:

		/* CP2520 pattern is unstable, temporarily use TPS4 instead */

		test_pattern = (force_tps4_for_cp2520 == 1) ?

		test_pattern = (link->dc->caps.force_dp_tps4_for_cp2520 == 1) ?

				DP_TEST_PATTERN_TRAINING_PATTERN4 :

				DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE;

		break;

drivers/gpu/drm/amd/display/dc/dc.h

+1 −0
Original line number Diff line number Diff line
@@ -76,6 +76,7 @@ struct dc_caps { 
	bool is_apu;

	bool dual_link_dvi;

	bool post_blend_color_processing;

	bool force_dp_tps4_for_cp2520;

};



struct dc_dcc_surface_param {