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Commit 282e45dc authored by Philipp Puschmann's avatar Philipp Puschmann Committed by Cyrille Pitchen
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mtd: spi-nor: Add support for mr25h128



Add Everspin mr25h128 16KB MRAM to the list of supported chips.

Signed-off-by: default avatarPhilipp Puschmann <pp@emlix.com>
Signed-off-by: default avatarCyrille Pitchen <cyrille.pitchen@wedev4u.fr>
parent d342b6a9
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@@ -13,6 +13,7 @@ Required properties:
                 at25df321a
                 at25df321a
                 at25df641
                 at25df641
                 at26df081a
                 at26df081a
                 mr25h128
                 mr25h256
                 mr25h256
                 mr25h10
                 mr25h10
                 mr25h40
                 mr25h40
+1 −0
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@@ -359,6 +359,7 @@ static const struct spi_device_id m25p_ids[] = {
	{"m25p32-nonjedec"},	{"m25p64-nonjedec"},	{"m25p128-nonjedec"},
	{"m25p32-nonjedec"},	{"m25p64-nonjedec"},	{"m25p128-nonjedec"},


	/* Everspin MRAMs (non-JEDEC) */
	/* Everspin MRAMs (non-JEDEC) */
	{ "mr25h128" }, /* 128 Kib, 40 MHz */
	{ "mr25h256" }, /* 256 Kib, 40 MHz */
	{ "mr25h256" }, /* 256 Kib, 40 MHz */
	{ "mr25h10" },  /*   1 Mib, 40 MHz */
	{ "mr25h10" },  /*   1 Mib, 40 MHz */
	{ "mr25h40" },  /*   4 Mib, 40 MHz */
	{ "mr25h40" },  /*   4 Mib, 40 MHz */
+1 −0
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@@ -968,6 +968,7 @@ static const struct flash_info spi_nor_ids[] = {
	{ "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },
	{ "f25l64qa", INFO(0x8c4117, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_HAS_LOCK) },


	/* Everspin */
	/* Everspin */
	{ "mr25h128", CAT25_INFO( 16 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
	{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
	{ "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
	{ "mr25h10",  CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
	{ "mr25h10",  CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
	{ "mr25h40",  CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
	{ "mr25h40",  CAT25_INFO(512 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },