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Commit 27e1c8ee authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/bjorn-pcie-cap' into next 

* pci/bjorn-pcie-cap:
  ath9k: Use standard #defines for PCIe Capability ASPM fields
  iwlwifi: Use standard #defines for PCIe Capability ASPM fields
  iwlwifi: collapse wrapper for pcie_capability_read_word()
  iwlegacy: Use standard #defines for PCIe Capability ASPM fields
  iwlegacy: collapse wrapper for pcie_capability_read_word()
  cxgb3: Use standard #defines for PCIe Capability ASPM fields
  PCI: Add standard PCIe Capability Link ASPM field names
  PCI/portdrv: Use PCI Express Capability accessors
  PCI: Use standard PCIe Capability Link register field names
  PCI: Add and use standard PCI-X Capability register names
parents 72e1e868 a875621e

drivers/net/ethernet/chelsio/cxgb3/t3_hw.c

+1 −1
Original line number Diff line number Diff line
@@ -3307,7 +3307,7 @@ static void config_pcie(struct adapter *adap) 
	    G_NUMFSTTRNSEQRX(t3_read_reg(adap, A_PCIE_MODE));

	log2_width = fls(adap->params.pci.width) - 1;

	acklat = ack_lat[log2_width][pldsize];

	if (val & 1)		/* check LOsEnable */

	if (val & PCI_EXP_LNKCTL_ASPM_L0S)	/* check LOsEnable */

		acklat += fst_trn_tx * 4;

	rpllmt = rpl_tmr[log2_width][pldsize] + fst_trn_rx * 4;

drivers/net/wireless/ath/ath9k/pci.c

+4 −4
Original line number Diff line number Diff line
@@ -125,23 +125,23 @@ static void ath_pci_aspm_init(struct ath_common *common) 


	if ((ath9k_hw_get_btcoex_scheme(ah) != ATH_BTCOEX_CFG_NONE) &&

	    (AR_SREV_9285(ah))) {

		/* Bluetooth coexistance requires disabling ASPM. */

		/* Bluetooth coexistence requires disabling ASPM. */

		pcie_capability_clear_word(pdev, PCI_EXP_LNKCTL,

			PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);

			PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);



		/*

		 * Both upstream and downstream PCIe components should

		 * have the same ASPM settings.

		 */

		pcie_capability_clear_word(parent, PCI_EXP_LNKCTL,

			PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);

			PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1);



		ath_info(common, "Disabling ASPM since BTCOEX is enabled\n");

		return;

	}



	pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &aspm);

	if (aspm & (PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1)) {

	if (aspm & (PCI_EXP_LNKCTL_ASPM_L0S | PCI_EXP_LNKCTL_ASPM_L1)) {

		ah->aspm_enabled = true;

		/* Initialize PCIe PM and SERDES registers. */

		ath9k_hw_configpcipowersave(ah, false);

drivers/net/wireless/iwlegacy/4965.h

+0 −4
Original line number Diff line number Diff line
@@ -917,10 +917,6 @@ struct il4965_scd_bc_tbl { 
/* PCI registers */

#define PCI_CFG_RETRY_TIMEOUT	0x041



/* PCI register values */

#define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01

#define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02



#define IL4965_DEFAULT_TX_RETRY  15



/* EEPROM */

drivers/net/wireless/iwlegacy/common.c

+5 −5
Original line number Diff line number Diff line
@@ -1183,9 +1183,10 @@ EXPORT_SYMBOL(il_power_update_mode); 
void

il_power_initialize(struct il_priv *il)

{

	u16 lctl = il_pcie_link_ctl(il);

	u16 lctl;



	il->power_data.pci_pm = !(lctl & PCI_CFG_LINK_CTRL_VAL_L0S_EN);

	pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);

	il->power_data.pci_pm = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);



	il->power_data.debug_sleep_level_override = -1;
@@ -4233,9 +4234,8 @@ il_apm_init(struct il_priv *il) 
	 *    power savings, even without L1.

	 */

	if (il->cfg->set_l0s) {

		lctl = il_pcie_link_ctl(il);

		if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) ==

		    PCI_CFG_LINK_CTRL_VAL_L1_EN) {

		pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &lctl);

		if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {

			/* L1-ASPM enabled; disable(!) L0S  */

			il_set_bit(il, CSR_GIO_REG,

				   CSR_GIO_REG_VAL_L0S_ENABLED);

drivers/net/wireless/iwlegacy/common.h

+0 −12
Original line number Diff line number Diff line
@@ -1829,14 +1829,6 @@ int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd); 
 * PCI						     *

 *****************************************************/



static inline u16

il_pcie_link_ctl(struct il_priv *il)

{

	u16 pci_lnk_ctl;

	pcie_capability_read_word(il->pci_dev, PCI_EXP_LNKCTL, &pci_lnk_ctl);

	return pci_lnk_ctl;

}



void il_bg_watchdog(unsigned long data);

u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);

__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
@@ -2434,10 +2426,6 @@ struct il_tfd { 
/* PCI registers */

#define PCI_CFG_RETRY_TIMEOUT	0x041



/* PCI register values */

#define PCI_CFG_LINK_CTRL_VAL_L0S_EN	0x01

#define PCI_CFG_LINK_CTRL_VAL_L1_EN	0x02



struct il_rate_info {

	u8 plcp;		/* uCode API:  RATE_6M_PLCP, etc. */

	u8 plcp_siso;		/* uCode API:  RATE_SISO_6M_PLCP, etc. */