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Commit 27aaa8ad authored Mar 27, 2018 by Michael Shych Committed by Wolfram Sang Apr 30, 2018

i2c: mlxcpld: Add capability register description to documentation



It adds capability register description to documentation.

Signed-off-by: Michael Shych <michaelsh@mellanox.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

parent ae4aa68d

Documentation/i2c/busses/i2c-mlxcpld

+4 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,10 @@ The next transaction types are supported:
		- Write Byte/Block.

		Registers:
		CPBLTY 0x0 - capability reg.
		Bits [6:5] - transaction length. b01 - 72B is supported,
		36B in other case.
		Bit 7 - SMBus block read support.
		CTRL 0x1 - control reg.
		Resets all the registers.
		HALF_CYC 0x4 - cycle reg.