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Commit 272966c0 authored by Paul Mundt's avatar Paul Mundt
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serial: sh-sci: Reorder the SCxTDR write after the TDxE clear. 



Under qemu there is a race between the TDxE read-and-clear and the SCxTDR
write. While on hardware it can be gauranteed that the read-and-clear
will happen prior to the character being written out, no such assumption
can be made under emulation. As this path happens with IRQs off and the
hardware itself doesn't care about the ordering, move the SCxTDR write
until after the read-and-clear.

Signed-off-by: default avatarVladimir Prus <vladimir@codesourcery.com>
Signed-off-by: default avatarPaul Mundt <lethal@linux-sh.org>
parent 5d52013c

arch/sh/kernel/early_printk.c

+1 −1
Original line number Diff line number Diff line
@@ -85,9 +85,9 @@ static void scif_sercon_putc(int c) 
	while (((sci_in(&scif_port, SCFDR) & EPK_FIFO_BITS) >= EPK_FIFO_SIZE))

		;



	sci_out(&scif_port, SCxTDR, c);

	sci_in(&scif_port, SCxSR);

	sci_out(&scif_port, SCxSR, 0xf3 & ~(0x20 | 0x40));

	sci_out(&scif_port, SCxTDR, c);



	while ((sci_in(&scif_port, SCxSR) & 0x40) == 0)

		;

drivers/serial/sh-sci.c

+1 −1
Original line number Diff line number Diff line
@@ -144,9 +144,9 @@ static void put_char(struct uart_port *port, char c) 
		status = sci_in(port, SCxSR);

	} while (!(status & SCxSR_TDxE(port)));



	sci_out(port, SCxTDR, c);

	sci_in(port, SCxSR);            /* Dummy read */

	sci_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));

	sci_out(port, SCxTDR, c);



	spin_unlock_irqrestore(&port->lock, flags);

}