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Commit 27251e00 authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
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ath9k: Enable D3/L1 ASPM fix for AR9462 



AR9462 requires this HW fix for ASPM to work properly.
Also, since WARegVal is used only for the AR8003 family,
use AR_SREV_9300_20_OR_LATER.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 65c1a4de

drivers/net/wireless/ath/ath9k/hw.c

+5 −6
Original line number Diff line number Diff line
@@ -574,18 +574,17 @@ static int __ath9k_hw_init(struct ath_hw *ah) 
	 * We need to do this to avoid RMW of this register. We cannot

	 * read the reg when chip is asleep.

	 */

	if (AR_SREV_9300_20_OR_LATER(ah)) {

		ah->WARegVal = REG_READ(ah, AR_WA);

		ah->WARegVal |= (AR_WA_D3_L1_DISABLE |

				 AR_WA_ASPM_TIMER_BASED_DISABLE);

	}



	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {

		ath_err(common, "Couldn't reset chip\n");

		return -EIO;

	}



	if (AR_SREV_9462(ah))

		ah->WARegVal &= ~AR_WA_D3_L1_DISABLE;



	if (AR_SREV_9565(ah)) {

		ah->WARegVal |= AR_WA_BIT22;

		REG_WRITE(ah, AR_WA, ah->WARegVal);