Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 26de4f1b authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Greg Kroah-Hartman
Browse files

serial: sh-sci: Add more register documentation 



Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: default avatarSimon Horman <horms@verge.net.au>
Acked-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent ff43da00

drivers/tty/serial/sh-sci.c

+15 −13
Original line number Diff line number Diff line
@@ -911,7 +911,7 @@ static irqreturn_t sci_rx_interrupt(int irq, void *ptr) 
		/* Disable future Rx interrupts */

		if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {

			disable_irq_nosync(irq);

			scr |= 0x4000;

			scr |= SCSCR_RDRQE;

		} else {

			scr &= ~SCSCR_RIE;

		}
@@ -1200,7 +1200,9 @@ static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl) 
		 */

		reg = sci_getreg(port, SCFCR);

		if (reg->size)

			serial_port_out(port, SCFCR, serial_port_in(port, SCFCR) | 1);

			serial_port_out(port, SCFCR,

					serial_port_in(port, SCFCR) |

					SCFCR_LOOP);

	}

}
@@ -1496,9 +1498,9 @@ static void sci_start_tx(struct uart_port *port) 
	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {

		u16 new, scr = serial_port_in(port, SCSCR);

		if (s->chan_tx)

			new = scr | 0x8000;

			new = scr | SCSCR_TDRQE;

		else

			new = scr & ~0x8000;

			new = scr & ~SCSCR_TDRQE;

		if (new != scr)

			serial_port_out(port, SCSCR, new);

	}
@@ -1525,7 +1527,7 @@ static void sci_stop_tx(struct uart_port *port) 
	ctrl = serial_port_in(port, SCSCR);



	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)

		ctrl &= ~0x8000;

		ctrl &= ~SCSCR_TDRQE;



	ctrl &= ~SCSCR_TIE;
@@ -1539,7 +1541,7 @@ static void sci_start_rx(struct uart_port *port) 
	ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);



	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)

		ctrl &= ~0x4000;

		ctrl &= ~SCSCR_RDRQE;



	serial_port_out(port, SCSCR, ctrl);

}
@@ -1551,7 +1553,7 @@ static void sci_stop_rx(struct uart_port *port) 
	ctrl = serial_port_in(port, SCSCR);



	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)

		ctrl &= ~0x4000;

		ctrl &= ~SCSCR_RDRQE;



	ctrl &= ~port_rx_irq_mask(port);
@@ -1614,7 +1616,7 @@ static void rx_timer_fn(unsigned long arg) 
	u16 scr = serial_port_in(port, SCSCR);



	if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {

		scr &= ~0x4000;

		scr &= ~SCSCR_RDRQE;

		enable_irq(s->irqs[SCIx_RXI_IRQ]);

	}

	serial_port_out(port, SCSCR, scr | SCSCR_RIE);
@@ -1871,13 +1873,13 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 
	smr_val = serial_port_in(port, SCSMR) & 3;



	if ((termios->c_cflag & CSIZE) == CS7)

		smr_val |= 0x40;

		smr_val |= SCSMR_CHR;

	if (termios->c_cflag & PARENB)

		smr_val |= 0x20;

		smr_val |= SCSMR_PE;

	if (termios->c_cflag & PARODD)

		smr_val |= 0x30;

		smr_val |= SCSMR_PE | SCSMR_ODD;

	if (termios->c_cflag & CSTOPB)

		smr_val |= 0x08;

		smr_val |= SCSMR_STOP;



	uart_update_timeout(port, termios->c_cflag, baud);
@@ -1885,7 +1887,7 @@ static void sci_set_termios(struct uart_port *port, struct ktermios *termios, 
		__func__, smr_val, cks, t, s->cfg->scscr);



	if (t >= 0) {

		serial_port_out(port, SCSMR, (smr_val & ~3) | cks);

		serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);

		serial_port_out(port, SCBRR, t);

		reg = sci_getreg(port, HSSRR);

		if (reg->size)

include/linux/serial_sci.h

+58 −35
Original line number Diff line number Diff line
@@ -10,45 +10,59 @@ 


#define SCIx_NOT_SUPPORTED	(-1)



#define SCSCR_TIE	(1 << 7)

#define SCSCR_RIE	(1 << 6)

#define SCSCR_TE	(1 << 5)

#define SCSCR_RE	(1 << 4)

#define SCSCR_REIE	(1 << 3)	/* not supported by all parts */

#define SCSCR_TOIE	(1 << 2)	/* not supported by all parts */

#define SCSCR_CKE1	(1 << 1)

#define SCSCR_CKE0	(1 << 0)



/* SCxSR SCI */

#define SCI_TDRE  0x80

#define SCI_RDRF  0x40

#define SCI_ORER  0x20

#define SCI_FER   0x10

#define SCI_PER   0x08

#define SCI_TEND  0x04

/* SCSMR (Serial Mode Register) */

#define SCSMR_CHR	(1 << 6)	/* 7-bit Character Length */

#define SCSMR_PE	(1 << 5)	/* Parity Enable */

#define SCSMR_ODD	(1 << 4)	/* Odd Parity */

#define SCSMR_STOP	(1 << 3)	/* Stop Bit Length */

#define SCSMR_CKS	0x0003		/* Clock Select */



/* Serial Control Register (@ = not supported by all parts) */

#define SCSCR_TIE	(1 << 7)	/* Transmit Interrupt Enable */

#define SCSCR_RIE	(1 << 6)	/* Receive Interrupt Enable */

#define SCSCR_TE	(1 << 5)	/* Transmit Enable */

#define SCSCR_RE	(1 << 4)	/* Receive Enable */

#define SCSCR_REIE	(1 << 3)	/* Receive Error Interrupt Enable @ */

#define SCSCR_TOIE	(1 << 2)	/* Timeout Interrupt Enable @ */

#define SCSCR_CKE1	(1 << 1)	/* Clock Enable 1 */

#define SCSCR_CKE0	(1 << 0)	/* Clock Enable 0 */

/* SCIFA/SCIFB only */

#define SCSCR_TDRQE	(1 << 15)	/* Tx Data Transfer Request Enable */

#define SCSCR_RDRQE	(1 << 14)	/* Rx Data Transfer Request Enable */



/* SCxSR (Serial Status Register) on SCI */

#define SCI_TDRE  0x80			/* Transmit Data Register Empty */

#define SCI_RDRF  0x40			/* Receive Data Register Full */

#define SCI_ORER  0x20			/* Overrun Error */

#define SCI_FER   0x10			/* Framing Error */

#define SCI_PER   0x08			/* Parity Error */

#define SCI_TEND  0x04			/* Transmit End */



#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)



/* SCxSR SCIF, HSCIF */

#define SCIF_ER    0x0080

#define SCIF_TEND  0x0040

#define SCIF_TDFE  0x0020

#define SCIF_BRK   0x0010

#define SCIF_FER   0x0008

#define SCIF_PER   0x0004

#define SCIF_RDF   0x0002

#define SCIF_DR    0x0001

/* SCxSR (Serial Status Register) on SCIF, HSCIF */

#define SCIF_ER    0x0080		/* Receive Error */

#define SCIF_TEND  0x0040		/* Transmission End */

#define SCIF_TDFE  0x0020		/* Transmit FIFO Data Empty */

#define SCIF_BRK   0x0010		/* Break Detect */

#define SCIF_FER   0x0008		/* Framing Error */

#define SCIF_PER   0x0004		/* Parity Error */

#define SCIF_RDF   0x0002		/* Receive FIFO Data Full */

#define SCIF_DR    0x0001		/* Receive Data Ready */



#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)



/* SCSPTR, optional */

#define SCSPTR_RTSIO	(1 << 7)

#define SCSPTR_CTSIO	(1 << 5)

#define SCSPTR_SPB2IO	(1 << 1)

#define SCSPTR_SPB2DT	(1 << 0)

/* SCFCR (FIFO Control Register) */

#define SCFCR_LOOP	(1 << 0)	/* Loopback Test */



/* SCSPTR (Serial Port Register), optional */

#define SCSPTR_RTSIO	(1 << 7)	/* Serial Port RTS Pin Input/Output */

#define SCSPTR_CTSIO	(1 << 5)	/* Serial Port CTS Pin Input/Output */

#define SCSPTR_SPB2IO	(1 << 1)	/* Serial Port Break Input/Output */

#define SCSPTR_SPB2DT	(1 << 0)	/* Serial Port Break Data */



/* HSSRR HSCIF */

#define HSCIF_SRE	0x8000

#define HSCIF_SRE	0x8000		/* Sampling Rate Register Enable */



enum {

	SCIx_PROBE_REGTYPE,
@@ -73,10 +87,19 @@ enum { 
 * Not all registers will exist on all parts.

 */

enum {

	SCSMR, SCBRR, SCSCR, SCxSR,

	SCFCR, SCFDR, SCxTDR, SCxRDR,

	SCLSR, SCTFDR, SCRFDR, SCSPTR,

	HSSRR,

	SCSMR,				/* Serial Mode Register */

	SCBRR,				/* Bit Rate Register */

	SCSCR,				/* Serial Control Register */

	SCxSR,				/* Serial Status Register */

	SCFCR,				/* FIFO Control Register */

	SCFDR,				/* FIFO Data Count Register */

	SCxTDR,				/* Transmit (FIFO) Data Register */

	SCxRDR,				/* Receive (FIFO) Data Register */

	SCLSR,				/* Line Status Register */

	SCTFDR,				/* Transmit FIFO Data Count Register */

	SCRFDR,				/* Receive FIFO Data Count Register */

	SCSPTR,				/* Serial Port Register */

	HSSRR,				/* Sampling Rate Register */



	SCIx_NR_REGS,

};