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Unverified Commit 268db077 authored by Paul Cercueil's avatar Paul Cercueil Committed by James Hogan
Browse files

clk: ingenic: support PLLs with no bypass bit 



The second PLL of the JZ4770 does not have a bypass bit.
This commit makes it possible to support it with the current common CGU
code.

Signed-off-by: default avatarPaul Cercueil <paul@crapouillou.net>
Acked-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Maarten ter Huurne <maarten@treewalker.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18479/


Signed-off-by: default avatarJames Hogan <jhogan@kernel.org>
parent e6cfa643

drivers/clk/ingenic/cgu.c

+2 −1
Original line number Diff line number Diff line
@@ -100,7 +100,8 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	n += pll_info->n_offset;

	od_enc = ctl >> pll_info->od_shift;

	od_enc &= GENMASK(pll_info->od_bits - 1, 0);

	bypass = !!(ctl & BIT(pll_info->bypass_bit));

	bypass = !pll_info->no_bypass_bit &&

		 !!(ctl & BIT(pll_info->bypass_bit));

	enable = !!(ctl & BIT(pll_info->enable_bit));



	if (bypass)

drivers/clk/ingenic/cgu.h

+2 −0
Original line number Diff line number Diff line
@@ -48,6 +48,7 @@ 
 * @bypass_bit: the index of the bypass bit in the PLL control register

 * @enable_bit: the index of the enable bit in the PLL control register

 * @stable_bit: the index of the stable bit in the PLL control register

 * @no_bypass_bit: if set, the PLL has no bypass functionality

 */

struct ingenic_cgu_pll_info {

	unsigned reg;
@@ -58,6 +59,7 @@ struct ingenic_cgu_pll_info { 
	u8 bypass_bit;

	u8 enable_bit;

	u8 stable_bit;

	bool no_bypass_bit;

};



/**