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Commit 26508cb7 authored Feb 08, 2014 by Markus Pargmann Committed by Shawn Guo Feb 09, 2014

ARM: dts: imx27 phycore pinctrl



Add pinctrl nodes and properties for phycore device nodes.

Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

parent 858db316

arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts

+26 −0

Original line number	Diff line number	Diff line
		@@ -19,6 +19,28 @@
		cs-gpios = <&gpio4 28 0>, <&gpio4 27 0>;
		};

		&iomuxc {
		imx27_phycore_rdk {
		pinctrl_uart1: uart1grp {
		fsl,pins = <
		MX27_PAD_UART1_TXD__UART1_TXD 0x0
		MX27_PAD_UART1_RXD__UART1_RXD 0x0
		MX27_PAD_UART1_CTS__UART1_CTS 0x0
		MX27_PAD_UART1_RTS__UART1_RTS 0x0
		>;
		};

		pinctrl_uart2: uart2grp {
		fsl,pins = <
		MX27_PAD_UART2_TXD__UART2_TXD 0x0
		MX27_PAD_UART2_RXD__UART2_RXD 0x0
		MX27_PAD_UART2_CTS__UART2_CTS 0x0
		MX27_PAD_UART2_RTS__UART2_RTS 0x0
		>;
		};
		};
		};

		&sdhci2 {
		bus-width = <4>;
		cd-gpios = <&gpio3 29 0>;
		@@ -29,11 +51,15 @@

		&uart1 {
		fsl,uart-has-rtscts;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart1>;
		status = "okay";
		};

		&uart2 {
		fsl,uart-has-rtscts;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_uart2>;
		status = "okay";
		};

arch/arm/boot/dts/imx27-phytec-phycore-som.dts

+39 −0

Original line number	Diff line number	Diff line
		@@ -135,11 +135,15 @@

		&fec {
		phy-reset-gpios = <&gpio3 30 0>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_fec1>;
		status = "okay";
		};

		&i2c2 {
		clock-frequency = <400000>;
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_i2c2>;
		status = "okay";

		at24@52 {
		@@ -159,6 +163,41 @@
		};
		};

		&iomuxc {
		imx27_phycore_som {
		pinctrl_fec1: fec1grp {
		fsl,pins = <
		MX27_PAD_SD3_CMD__FEC_TXD0 0x0
		MX27_PAD_SD3_CLK__FEC_TXD1 0x0
		MX27_PAD_ATA_DATA0__FEC_TXD2 0x0
		MX27_PAD_ATA_DATA1__FEC_TXD3 0x0
		MX27_PAD_ATA_DATA2__FEC_RX_ER 0x0
		MX27_PAD_ATA_DATA3__FEC_RXD1 0x0
		MX27_PAD_ATA_DATA4__FEC_RXD2 0x0
		MX27_PAD_ATA_DATA5__FEC_RXD3 0x0
		MX27_PAD_ATA_DATA6__FEC_MDIO 0x0
		MX27_PAD_ATA_DATA7__FEC_MDC 0x0
		MX27_PAD_ATA_DATA8__FEC_CRS 0x0
		MX27_PAD_ATA_DATA9__FEC_TX_CLK 0x0
		MX27_PAD_ATA_DATA10__FEC_RXD0 0x0
		MX27_PAD_ATA_DATA11__FEC_RX_DV 0x0
		MX27_PAD_ATA_DATA12__FEC_RX_CLK 0x0
		MX27_PAD_ATA_DATA13__FEC_COL 0x0
		MX27_PAD_ATA_DATA14__FEC_TX_ER 0x0
		MX27_PAD_ATA_DATA15__FEC_TX_EN 0x0
		MX27_PAD_SSI3_TXDAT__GPIO3_30 0x0 /* FEC RST */
		>;
		};

		pinctrl_i2c2: i2c2grp {
		fsl,pins = <
		MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
		MX27_PAD_I2C2_SCL__I2C2_SCL 0x0
		>;
		};
		};
		};

		&nfc {
		nand-bus-width = <8>;
		nand-ecc-mode = "hw";