drm/radeon: fix pixcache and purge/cache flushing registers (259434ac) · Commits · e / devices / android_kernel_teracube_emerald

drivers/char/drm/r300_reg.h

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -1346,7 +1346,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
	/* Guess by Vladimir.		/* Guess by Vladimir.
	* Set to 0A before 3D operations, set to 02 afterwards.		* Set to 0A before 3D operations, set to 02 afterwards.
	*/		*/
	#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C		/#define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C/
	# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002		# define R300_RB3D_DSTCACHE_UNKNOWN_02 0x00000002
	# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A		# define R300_RB3D_DSTCACHE_UNKNOWN_0A 0x0000000A

drivers/char/drm/radeon_cp.c

+29 −9

Original line number	Original line	Diff line number	Diff line
	@@ -161,6 +161,7 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)

	dev_priv->stats.boxes \|= RADEON_BOX_WAIT_IDLE;		dev_priv->stats.boxes \|= RADEON_BOX_WAIT_IDLE;

			if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
	tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);		tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
	tmp \|= RADEON_RB3D_DC_FLUSH_ALL;		tmp \|= RADEON_RB3D_DC_FLUSH_ALL;
	RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);		RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
	@@ -172,6 +173,25 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
	}		}
	DRM_UDELAY(1);		DRM_UDELAY(1);
	}		}
			} else {
			/* 3D */
			tmp = RADEON_READ(R300_RB3D_DSTCACHE_CTLSTAT);
			tmp \|= RADEON_RB3D_DC_FLUSH_ALL;
			RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);

			/* 2D */
			tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
			tmp \|= RADEON_RB3D_DC_FLUSH_ALL;
			RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);

			for (i = 0; i < dev_priv->usec_timeout; i++) {
			if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
			& RADEON_RB3D_DC_BUSY)) {
			return 0;
			}
			DRM_UDELAY(1);
			}
			}

	#if RADEON_FIFO_DEBUG		#if RADEON_FIFO_DEBUG
	DRM_ERROR("failed!\n");		DRM_ERROR("failed!\n");

drivers/char/drm/radeon_drv.h

+35 −8

Original line number	Original line	Diff line number	Diff line
	@@ -659,11 +659,18 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
	# define RADEON_RB3D_ZC_FREE (1 << 2)		# define RADEON_RB3D_ZC_FREE (1 << 2)
	# define RADEON_RB3D_ZC_FLUSH_ALL 0x5		# define RADEON_RB3D_ZC_FLUSH_ALL 0x5
	# define RADEON_RB3D_ZC_BUSY (1 << 31)		# define RADEON_RB3D_ZC_BUSY (1 << 31)
			#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
			# define R300_ZC_FLUSH (1 << 0)
			# define R300_ZC_FREE (1 << 1)
			# define R300_ZC_FLUSH_ALL 0x3
			# define R300_ZC_BUSY (1 << 31)
	#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c		#define RADEON_RB3D_DSTCACHE_CTLSTAT 0x325c
	# define RADEON_RB3D_DC_FLUSH (3 << 0)		# define RADEON_RB3D_DC_FLUSH (3 << 0)
	# define RADEON_RB3D_DC_FREE (3 << 2)		# define RADEON_RB3D_DC_FREE (3 << 2)
	# define RADEON_RB3D_DC_FLUSH_ALL 0xf		# define RADEON_RB3D_DC_FLUSH_ALL 0xf
	# define RADEON_RB3D_DC_BUSY (1 << 31)		# define RADEON_RB3D_DC_BUSY (1 << 31)
			#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
			# define R300_RB3D_DC_FINISH (1 << 4)
	#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c		#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
	# define RADEON_Z_TEST_MASK (7 << 4)		# define RADEON_Z_TEST_MASK (7 << 4)
	# define RADEON_Z_TEST_ALWAYS (7 << 4)		# define RADEON_Z_TEST_ALWAYS (7 << 4)
	@@ -1178,23 +1185,43 @@ do { \
	} while (0)		} while (0)

	#define RADEON_FLUSH_CACHE() do { \		#define RADEON_FLUSH_CACHE() do { \
			if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
	OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \		OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
	OUT_RING(RADEON_RB3D_DC_FLUSH); \		OUT_RING(RADEON_RB3D_DC_FLUSH); \
			} else { \
			OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
			OUT_RING(RADEON_RB3D_DC_FLUSH); \
			} \
	} while (0)		} while (0)

	#define RADEON_PURGE_CACHE() do { \		#define RADEON_PURGE_CACHE() do { \
			if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
	OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \		OUT_RING(CP_PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); \
	OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \		OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
			} else { \
			OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
			OUT_RING(RADEON_RB3D_DC_FLUSH_ALL); \
			} \
	} while (0)		} while (0)

	#define RADEON_FLUSH_ZCACHE() do { \		#define RADEON_FLUSH_ZCACHE() do { \
			if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
	OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \		OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
	OUT_RING(RADEON_RB3D_ZC_FLUSH); \		OUT_RING(RADEON_RB3D_ZC_FLUSH); \
			} else { \
			OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0)); \
			OUT_RING(R300_ZC_FLUSH); \
			} \
	} while (0)		} while (0)

	#define RADEON_PURGE_ZCACHE() do { \		#define RADEON_PURGE_ZCACHE() do { \
			if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) { \
	OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \		OUT_RING(CP_PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); \
	OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \		OUT_RING(RADEON_RB3D_ZC_FLUSH_ALL); \
			} else { \
			OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); \
			OUT_RING(R300_ZC_FLUSH_ALL); \
			} \
	} while (0)		} while (0)

	/* ================================================================		/* ================================================================