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Commit 25501837 authored Mar 28, 2017 by David S. Miller

Merge branch 'dsa-mv88e6xxx-fix-chip-definitions'



Vivien Didelot says:

====================
net: dsa: fix chip definitions

The definitions of some of the mv88e6xxx_ops and mv88e6xxx_info
structures are misordered and erroneous for 88E6191 and 88E6391.

This patch series cleans that up.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>

parents c552a50e 63709570

drivers/net/dsa/mv88e6xxx/chip.c

+78 −108

Original line number	Original line	Diff line number	Diff line
	@@ -2944,6 +2944,37 @@ static const struct mv88e6xxx_ops mv88e6131_ops = {
	.reset = mv88e6185_g1_reset,		.reset = mv88e6185_g1_reset,
	};		};

			static const struct mv88e6xxx_ops mv88e6141_ops = {
			/* MV88E6XXX_FAMILY_6341 */
			.get_eeprom = mv88e6xxx_g2_get_eeprom8,
			.set_eeprom = mv88e6xxx_g2_set_eeprom8,
			.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
			.phy_read = mv88e6xxx_g2_smi_phy_read,
			.phy_write = mv88e6xxx_g2_smi_phy_write,
			.port_set_link = mv88e6xxx_port_set_link,
			.port_set_duplex = mv88e6xxx_port_set_duplex,
			.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
			.port_set_speed = mv88e6390_port_set_speed,
			.port_tag_remap = mv88e6095_port_tag_remap,
			.port_set_frame_mode = mv88e6351_port_set_frame_mode,
			.port_set_egress_floods = mv88e6352_port_set_egress_floods,
			.port_set_ether_type = mv88e6351_port_set_ether_type,
			.port_jumbo_config = mv88e6165_port_jumbo_config,
			.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
			.port_pause_config = mv88e6097_port_pause_config,
			.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
			.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
			.stats_snapshot = mv88e6390_g1_stats_snapshot,
			.stats_get_sset_count = mv88e6320_stats_get_sset_count,
			.stats_get_strings = mv88e6320_stats_get_strings,
			.stats_get_stats = mv88e6390_stats_get_stats,
			.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
			.g1_set_egress_port = mv88e6390_g1_set_egress_port,
			.watchdog_ops = &mv88e6390_watchdog_ops,
			.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
			.reset = mv88e6352_g1_reset,
			};

	static const struct mv88e6xxx_ops mv88e6161_ops = {		static const struct mv88e6xxx_ops mv88e6161_ops = {
	/* MV88E6XXX_FAMILY_6165 */		/* MV88E6XXX_FAMILY_6165 */
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,		.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	@@ -3347,6 +3378,37 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
	.reset = mv88e6352_g1_reset,		.reset = mv88e6352_g1_reset,
	};		};

			static const struct mv88e6xxx_ops mv88e6341_ops = {
			/* MV88E6XXX_FAMILY_6341 */
			.get_eeprom = mv88e6xxx_g2_get_eeprom8,
			.set_eeprom = mv88e6xxx_g2_set_eeprom8,
			.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
			.phy_read = mv88e6xxx_g2_smi_phy_read,
			.phy_write = mv88e6xxx_g2_smi_phy_write,
			.port_set_link = mv88e6xxx_port_set_link,
			.port_set_duplex = mv88e6xxx_port_set_duplex,
			.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
			.port_set_speed = mv88e6390_port_set_speed,
			.port_tag_remap = mv88e6095_port_tag_remap,
			.port_set_frame_mode = mv88e6351_port_set_frame_mode,
			.port_set_egress_floods = mv88e6352_port_set_egress_floods,
			.port_set_ether_type = mv88e6351_port_set_ether_type,
			.port_jumbo_config = mv88e6165_port_jumbo_config,
			.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
			.port_pause_config = mv88e6097_port_pause_config,
			.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
			.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
			.stats_snapshot = mv88e6390_g1_stats_snapshot,
			.stats_get_sset_count = mv88e6320_stats_get_sset_count,
			.stats_get_strings = mv88e6320_stats_get_strings,
			.stats_get_stats = mv88e6390_stats_get_stats,
			.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
			.g1_set_egress_port = mv88e6390_g1_set_egress_port,
			.watchdog_ops = &mv88e6390_watchdog_ops,
			.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
			.reset = mv88e6352_g1_reset,
			};

	static const struct mv88e6xxx_ops mv88e6350_ops = {		static const struct mv88e6xxx_ops mv88e6350_ops = {
	/* MV88E6XXX_FAMILY_6351 */		/* MV88E6XXX_FAMILY_6351 */
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,		.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	@@ -3436,68 +3498,6 @@ static const struct mv88e6xxx_ops mv88e6352_ops = {
	.reset = mv88e6352_g1_reset,		.reset = mv88e6352_g1_reset,
	};		};

	static const struct mv88e6xxx_ops mv88e6141_ops = {
	/* MV88E6XXX_FAMILY_6341 */
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
	.port_jumbo_config = mv88e6165_port_jumbo_config,
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
	.port_pause_config = mv88e6097_port_pause_config,
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
	.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
	.g1_set_egress_port = mv88e6390_g1_set_egress_port,
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
	.reset = mv88e6352_g1_reset,
	};

	static const struct mv88e6xxx_ops mv88e6341_ops = {
	/* MV88E6XXX_FAMILY_6341 */
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6095_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
	.port_jumbo_config = mv88e6165_port_jumbo_config,
	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
	.port_pause_config = mv88e6097_port_pause_config,
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
	.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
	.g1_set_egress_port = mv88e6390_g1_set_egress_port,
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
	.reset = mv88e6352_g1_reset,
	};

	static const struct mv88e6xxx_ops mv88e6390_ops = {		static const struct mv88e6xxx_ops mv88e6390_ops = {
	/* MV88E6XXX_FAMILY_6390 */		/* MV88E6XXX_FAMILY_6390 */
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,		.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	@@ -3563,36 +3563,6 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = {
	.reset = mv88e6352_g1_reset,		.reset = mv88e6352_g1_reset,
	};		};

	static const struct mv88e6xxx_ops mv88e6391_ops = {
	/* MV88E6XXX_FAMILY_6390 */
	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
	.phy_read = mv88e6xxx_g2_smi_phy_read,
	.phy_write = mv88e6xxx_g2_smi_phy_write,
	.port_set_link = mv88e6xxx_port_set_link,
	.port_set_duplex = mv88e6xxx_port_set_duplex,
	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
	.port_set_speed = mv88e6390_port_set_speed,
	.port_tag_remap = mv88e6390_port_tag_remap,
	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
	.port_set_ether_type = mv88e6351_port_set_ether_type,
	.port_pause_config = mv88e6390_port_pause_config,
	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
	.stats_snapshot = mv88e6390_g1_stats_snapshot,
	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
	.stats_get_strings = mv88e6320_stats_get_strings,
	.stats_get_stats = mv88e6390_stats_get_stats,
	.g1_set_cpu_port = mv88e6390_g1_set_cpu_port,
	.g1_set_egress_port = mv88e6390_g1_set_egress_port,
	.watchdog_ops = &mv88e6390_watchdog_ops,
	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
	.reset = mv88e6352_g1_reset,
	};

	static const struct mv88e6xxx_info mv88e6xxx_table[] = {		static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	[MV88E6085] = {		[MV88E6085] = {
	.prod_num = PORT_SWITCH_ID_PROD_NUM_6085,		.prod_num = PORT_SWITCH_ID_PROD_NUM_6085,
	@@ -3674,6 +3644,21 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	.ops = &mv88e6131_ops,		.ops = &mv88e6131_ops,
	},		},

			[MV88E6141] = {
			.prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
			.family = MV88E6XXX_FAMILY_6341,
			.name = "Marvell 88E6341",
			.num_databases = 4096,
			.num_ports = 6,
			.port_base_addr = 0x10,
			.global1_addr = 0x1b,
			.age_time_coeff = 3750,
			.atu_move_port_mask = 0x1f,
			.tag_protocol = DSA_TAG_PROTO_EDSA,
			.flags = MV88E6XXX_FLAGS_FAMILY_6341,
			.ops = &mv88e6141_ops,
			},

	[MV88E6161] = {		[MV88E6161] = {
	.prod_num = PORT_SWITCH_ID_PROD_NUM_6161,		.prod_num = PORT_SWITCH_ID_PROD_NUM_6161,
	.family = MV88E6XXX_FAMILY_6165,		.family = MV88E6XXX_FAMILY_6165,
	@@ -3831,7 +3816,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	.atu_move_port_mask = 0x1f,		.atu_move_port_mask = 0x1f,
	.tag_protocol = DSA_TAG_PROTO_DSA,		.tag_protocol = DSA_TAG_PROTO_DSA,
	.flags = MV88E6XXX_FLAGS_FAMILY_6390,		.flags = MV88E6XXX_FLAGS_FAMILY_6390,
	.ops = &mv88e6391_ops,		.ops = &mv88e6191_ops,
	},		},

	[MV88E6240] = {		[MV88E6240] = {
	@@ -3898,21 +3883,6 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
	.ops = &mv88e6321_ops,		.ops = &mv88e6321_ops,
	},		},

	[MV88E6141] = {
	.prod_num = PORT_SWITCH_ID_PROD_NUM_6141,
	.family = MV88E6XXX_FAMILY_6341,
	.name = "Marvell 88E6341",
	.num_databases = 4096,
	.num_ports = 6,
	.port_base_addr = 0x10,
	.global1_addr = 0x1b,
	.age_time_coeff = 3750,
	.atu_move_port_mask = 0x1f,
	.tag_protocol = DSA_TAG_PROTO_EDSA,
	.flags = MV88E6XXX_FLAGS_FAMILY_6341,
	.ops = &mv88e6141_ops,
	},

	[MV88E6341] = {		[MV88E6341] = {
	.prod_num = PORT_SWITCH_ID_PROD_NUM_6341,		.prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
	.family = MV88E6XXX_FAMILY_6341,		.family = MV88E6XXX_FAMILY_6341,