Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 2538090c authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/pp: Delete get_xclk function in powerplay (v2) 



use asic's callback function get_xclk in amdgpu

v2: squash in removal of leftover debug info
(drm/amd/pp: Delete debug info in smu7_hwmgr.c) (Rex)

Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarEvan Quan <evan.quan@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c7d30b40

drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c

+1 −4
Original line number Diff line number Diff line
@@ -715,12 +715,9 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device, 
		return -EINVAL;



	mode_info = info->mode_info;

	if (mode_info) {

	if (mode_info)

		/* if the displays are off, vblank time is max */

		mode_info->vblank_time_us = 0xffffffff;

		/* always set the reference clock */

		mode_info->ref_clock = adev->clock.spll.reference_freq;

	}



	if (!amdgpu_device_has_dc_support(adev)) {

		struct amdgpu_crtc *amdgpu_crtc;

drivers/gpu/drm/amd/include/cgs_common.h

+0 −1
Original line number Diff line number Diff line
@@ -106,7 +106,6 @@ struct cgs_firmware_info { 


struct cgs_mode_info {

	uint32_t		refresh_rate;

	uint32_t		ref_clock;

	uint32_t		vblank_time_us;

};

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+2 −25
Original line number Diff line number Diff line
@@ -891,30 +891,6 @@ static int smu7_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) 
	return 0;

}



uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr)

{

	uint32_t reference_clock, tmp;

	struct cgs_display_info info = {0};

	struct cgs_mode_info mode_info = {0};



	info.mode_info = &mode_info;



	tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL_2, MUX_TCLK_TO_XCLK);



	if (tmp)

		return TCLK;



	cgs_get_active_displays_info(hwmgr->device, &info);

	reference_clock = mode_info.ref_clock;



	tmp = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_CLKPIN_CNTL, XTALIN_DIVIDE);



	if (0 != tmp)

		return reference_clock / 4;



	return reference_clock;

}



static int smu7_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr)

{
@@ -3970,7 +3946,8 @@ static int smu7_program_display_gap(struct pp_hwmgr *hwmgr) 
	display_gap = PHM_SET_FIELD(display_gap, CG_DISPLAY_GAP_CNTL, DISP_GAP, (num_active_displays > 0) ? DISPLAY_GAP_VBLANK_OR_WM : DISPLAY_GAP_IGNORE);

	cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL, display_gap);



	ref_clock = mode_info.ref_clock;

	ref_clock =  amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);



	refresh_rate = mode_info.refresh_rate;



	if (0 == refresh_rate)

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.h

+0 −1
Original line number Diff line number Diff line
@@ -361,7 +361,6 @@ enum SMU7_I2CLineID { 
#define SMU7_I2C_DDCVGACLK         0x4d



#define SMU7_UNUSED_GPIO_PIN       0x7F

uint32_t smu7_get_xclk(struct pp_hwmgr *hwmgr);

uint8_t smu7_get_sleep_divider_id_from_clock(uint32_t clock,

		uint32_t clock_insr);

#endif

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_thermal.c

+2 −2
Original line number Diff line number Diff line
@@ -95,7 +95,7 @@ int smu7_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) 
	if (tach_period == 0)

		return -EINVAL;



	crystal_clock_freq = smu7_get_xclk(hwmgr);

	crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);



	*speed = 60 * crystal_clock_freq * 10000 / tach_period;
@@ -267,7 +267,7 @@ int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) 
	if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))

		smu7_fan_ctrl_stop_smc_fan_control(hwmgr);



	crystal_clock_freq = smu7_get_xclk(hwmgr);

	crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);



	tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);