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Commit 243fee32 authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm/radix: Move the functions that does the actual tlbie closer 



No functionality change. Just code movement to ease code changes later

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent 99491e2d

arch/powerpc/mm/tlb-radix.c

+32 −32
Original line number Diff line number Diff line
@@ -119,6 +119,38 @@ static inline void __tlbie_pid(unsigned long pid, unsigned long ric) 
	trace_tlbie(0, 0, rb, rs, ric, prs, r);

}



static inline void __tlbiel_va(unsigned long va, unsigned long pid,

			       unsigned long ap, unsigned long ric)

{

	unsigned long rb,rs,prs,r;



	rb = va & ~(PPC_BITMASK(52, 63));

	rb |= ap << PPC_BITLSHIFT(58);

	rs = pid << PPC_BITLSHIFT(31);

	prs = 1; /* process scoped */

	r = 1;   /* raidx format */



	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)

		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");

	trace_tlbie(0, 1, rb, rs, ric, prs, r);

}



static inline void __tlbie_va(unsigned long va, unsigned long pid,

			      unsigned long ap, unsigned long ric)

{

	unsigned long rb,rs,prs,r;



	rb = va & ~(PPC_BITMASK(52, 63));

	rb |= ap << PPC_BITLSHIFT(58);

	rs = pid << PPC_BITLSHIFT(31);

	prs = 1; /* process scoped */

	r = 1;   /* raidx format */



	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)

		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");

	trace_tlbie(0, 0, rb, rs, ric, prs, r);

}



/*

 * We use 128 set in radix mode and 256 set in hpt mode.

 */
@@ -171,22 +203,6 @@ static inline void _tlbie_pid(unsigned long pid, unsigned long ric) 
	asm volatile("eieio; tlbsync; ptesync": : :"memory");

}



static inline void __tlbiel_va(unsigned long va, unsigned long pid,

			       unsigned long ap, unsigned long ric)

{

	unsigned long rb,rs,prs,r;



	rb = va & ~(PPC_BITMASK(52, 63));

	rb |= ap << PPC_BITLSHIFT(58);

	rs = pid << PPC_BITLSHIFT(31);

	prs = 1; /* process scoped */

	r = 1;   /* raidx format */



	asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)

		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");

	trace_tlbie(0, 1, rb, rs, ric, prs, r);

}



static inline void __tlbiel_va_range(unsigned long start, unsigned long end,

				    unsigned long pid, unsigned long page_size,

				    unsigned long psize)
@@ -219,22 +235,6 @@ static inline void _tlbiel_va_range(unsigned long start, unsigned long end, 
	asm volatile("ptesync": : :"memory");

}



static inline void __tlbie_va(unsigned long va, unsigned long pid,

			     unsigned long ap, unsigned long ric)

{

	unsigned long rb,rs,prs,r;



	rb = va & ~(PPC_BITMASK(52, 63));

	rb |= ap << PPC_BITLSHIFT(58);

	rs = pid << PPC_BITLSHIFT(31);

	prs = 1; /* process scoped */

	r = 1;   /* raidx format */



	asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)

		     : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");

	trace_tlbie(0, 0, rb, rs, ric, prs, r);

}



static inline void __tlbie_va_range(unsigned long start, unsigned long end,

				    unsigned long pid, unsigned long page_size,

				    unsigned long psize)